Publications

Summary: IEEE TCAD (21), DAC (11), ICCAD (15), etc.

Journal & Conference Papers

Selected Preprints

• Haoyu Yang, Shuhe Li, Cyrus Tabery, Bingqing Lin, Bei Yu, “Bridging the Gap Between Layout Pattern Sampling and Hotspot Detection via Batch Active Learning”. (arXiv)

• Qianru Zhang, Meng Zhang, Tinghuan Chen, Zhifei Sun, Yuzhe Ma, Bei Yu, “Recent Advances in Convolutional Neural Network Acceleration”.

• Yuzhe Ma, Subhendu Roy, Jin Miao, Jiamin Chen, Bei Yu, “Cross-layer Optimization for High Speed Adders: A Pareto Driven Machine Learning Approach”. (arXiv)

Accepted

• [J] Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan, “A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (preprint)

• [J] Xingquan Li, Bei Yu, Jiaojiao Ou, Jianli Chen, David Z. Pan, Wenxing Zhu, “Graph Based Redundant Via Insertion and Guiding Template Assignment for DSA-MP”, accepted by IEEE Transactions on Very Large Scale Integration Systems (TVLSI). (preprint)

• [J] Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young, “Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (preprint) (code)

• [J] Derong Liu, Bei Yu, Vinicius Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan, “Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (preprint)

• [J] Song Chen, Qi Xu, Bei Yu, “Adaptive 3D-IC TSV Fault Tolerance Structure Generation”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (preprint)

• [J] Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu, “RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (preprint)

• [J] Jian Kuang, Evangeline F. Y. Young, Bei Yu, “CRMA: Incorporating Cut Redistribution with Mask Assignment to Enable the Fabrication of 1D Gridded Design”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (preprint)

• [J] Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan, “Provably Secure Camouflaging Strategy for IC Protection”, accepted by IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD). (preprint)

2018

• [J32] Yibo Lin, Bei Yu, Meng Li, David Z. Pan, “Layout Synthesis for Topological Quantum Circuits with 1D and 2D Architectures”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 8, pp. 1574–1587, 2018. (paper)

• [J31] Shiyan Hu, Bei Yu, Huafeng Yu, “Guest Editorial on Special Issue on Sustainable Cyber-Physical Systems”, IEEE Transactions on Sustainable Computing (TSUSC), vol. 3, no. 2, pp. 58–59, 2018.

• [J30] Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan, “MrDP: Multiple-row Detailed Placement of Heterogeneous-sized Cells for Advanced Nodes”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 6, pp. 1237–1250, 2018. (paper)

• [J29] Jin Miao, Meng Li, Subhendu Roy, Yuzhe Ma, Bei Yu, “SD-PUF: Spliced Digital Physical Unclonable Function”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 5, pp. 927–940, 2018. (paper)

• [J28] Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan, “TILA-S: Timing-Driven Incremental Layer Assignment Avoiding Slew Violations”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 1, pp. 231–244, 2018. (paper)

• [J27] Xiaotao Jia, Yici Cai, Qiang Zhou, Bei Yu, “A Multi-Commodity Flow based Detailed Router with Efficient Acceleration Techniques”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 37, no. 1, pp. 217–230, 2018. (paper)

• [C75] Bei Yu, Haoyu Yang, “Deep Mask Optimization: From Detection to Automatic Generation”, IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), Qingdao, Oct. 31–Nov. 3, 2018. (Invited Paper)

• [C74] Hao Geng, Haoyu Yang, Bei Yu, Xingquan Li, Xuan Zeng, “Sparse VLSI Layout Feature Extraction: A Dictionary Learning Approach”, IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Hong Kong, July 9–11, 2018. (Invited Paper)

• [C73] Haoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young, “GAN-OPC: Mask Optimization with Lithography-guided Generative Adversarial Nets”, ACM/IEEE Design Automation Conference (DAC), pp. 131:1–131:6, San Francisco, CA, June 24–28, 2018. (paper) (slides) (poster)

• [C72] Haocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu, “Routability-Driven and Fence-Aware Legalization for Mixed-Cell-Height Circuits”, ACM/IEEE Design Automation Conference (DAC), pp. 150:1–150:6, San Francisco, CA, June 24–28, 2018. (paper) (slides) (poster)

• [C71] Fengxian Jiao, Sheqin Dong, Bei Yu, Bing Li, Ulf Schlichtmann, “Thermal-Aware Placement and Routing for 3D Optical Networks-on-Chips”, IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–4, Florence, May 27–30, 2018. (paper)

• [C70] Qi Xu, Song Chen, Bei Yu, Feng Wu, “Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC”, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 451–454, Chicago, IL, May 23–25, 2018. (paper)

• [C69] Wei Ye, Meng Li, Kai Zhong, Bei Yu, David Z. Pan, “Power Grid Reduction by Sparse Convex Optimization”, ACM International Symposium on Physical Design (ISPD), pp. 60–67, Monterey, CA, Mar. 25–28, 2018. (paper) (slides)

• [C68] Grace Li Zhang, Bing Li, Bei Yu, David Z. Pan, Ulf Schlichtmann, “TimingCamouflage: Improving Circuit Security against Counterfeiting by Unconventional Timing”, IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), pp. 91–96, Dresden, Mar. 19–23, 2018. (paper)

• [C67] Meng Li, Bei Yu, Yibo Lin, Xiaoqing Xu, Wuxi Li, David Z. Pan, “A Practical Split Manufacturing Framework for Trojan Prevention via Simultaneous Wire Lifting and Cell Insertion”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), pp. 265–270, Jeju Island, Jan. 22–25, 2018. (paper) (slides)

2017

• [J26] Haoyu Yang, Luyang Luo, Jing Su, Chenxi Lin, Bei Yu, “Imbalance Aware Lithography Hotspot Detection: A Deep Learning Approach”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 16, no. 3, 033504, 2017. (paper)

• [J25] Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick, David Z. Pan, “Triple/Quadruple Patterning Layout Decomposition via Novel Linear Programming and Iterative Rounding”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 16, no. 2, 023507, 2017. (paper)

• [J24] Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan, “Incremental Layer Assignment for Timing Optimization”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 22, no. 75, pp. 75:1–75:25, 2017. (paper)

• [J23] Yibo Lin, Bei Yu, David Z. Pan, “High Performance Dummy Fill Insertion with Coupling and Uniformity Constraints”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 9, pp. 1532–1544, 2017. (paper)

• [J22] Qi Xu, Song Chen, Xiaodong Xu, Bei Yu, “Clustered Fault Tolerance TSV Planning for 3D Integrated Circuits”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 8, pp. 1287–1300, 2017. (paper)

• [J21] Yibo Lin, Bei Yu, Biying Xu, David Z. Pan, “Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 7, pp. 1140–1152, 2017. (paper)

• [J20] Vinicius Livramento, Derong Liu, Salim Chowdhury, Bei Yu, Xiaoqing Xu, David Z. Pan, Jose Luis Guntzel, Luiz C. V. dos Santos, “Incremental Layer Assignment Driven by an External Signoff Timing Engine”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 36, no. 7, pp. 1126–1139, 2017. (paper)

• [J19] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan, “Stitch Aware Detailed Placement for Multiple E-Beam Lithography”, Integration, the VLSI Journal, vol. 58, June, pp. 47–54, 2017. (paper) (Best Paper Award)

• [J18] Meikang Qiu, Saurabh Garg, Rujkumar Buyya, Bei Yu, Shiyan Hu, “Special Issue on Scalable Cyber-Physical Systems”, Journal of Parallel and Distributed Computing (JPDC), vol. 103, pp. 1–2, May 2017.

• [J17] Bingqing Lin, Bei Yu, “Smart Building Uncertainty Analysis via Adaptive Lasso”, IET Cyber-Physical Systems: Theory & Applications (IET-CPS), vol. 2, no. 1, pp. 1–7, 2017. (paper)

• [C66] Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu, “Clock-Aware UltraScale FPGA Placement with Machine Learning Routability Prediction”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 929–936, Irvine, CA, Nov. 13–16, 2017. (paper) (slides) (Invited Paper)

• [C65] Yuzhe Ma, Jhih-Rong Gao, Jian Kuang, Jin Miao, Bei Yu, “A Unified Framework for Simultaneous Layout Decomposition and Mask Optimization”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 81–88, Irvine, CA, Nov. 13–16, 2017. (paper) (slides)

• [C64] Yuzhe Ma, Xuan Zeng, Bei Yu, “Methodologies for Layout Decomposition and Mask Optimization: A Systematic Review”, IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Abu Dhabi, UAE, Oct. 23–25, 2017. (paper) (Invited Paper)

• [C63] Cheng Zhuo, Bei Yu, Di Gao, “Accelerating Chip Design with Machine Learning: From Pre-Silicon to Post-Silicon”, IEEE International System-on-Chip Conference (SOCC), pp. 227–232, Munich, Germany, September 5–8, 2017. (paper) (Invited Paper)

• [C62] Haoyu Yang, Yajun Lin, Bei Yu, Evangeline F. Y. Young, “Lithography Hotspot Detection: From Shallow To Deep Learning”, IEEE International System-on-Chip Conference (SOCC), pp. 233–238, Munich, Germany, September 5–8, 2017. (paper) (Invited Paper)

• [C61] Subhendu Roy, Yuzhe Ma, Jin Miao, Bei Yu, “A Learning Bridge from Architectural Synthesis to Physical Design for Exploring Power Efficient High-Performance Adders”, IEEE International Symposium on Low Power Electronics and Design (ISLPED), Taipei, July 24–26, 2017. (paper) (slides)

• [C60] Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young, “Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning”, ACM/IEEE Design Automation Conference (DAC), pp. 62:1–62:6, Austin, TX, June 18–22, 2017. (paper) (slides) (poster)

• [C59] Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu, “Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design”, ACM/IEEE Design Automation Conference (DAC), pp. 70:1–70:6, Austin, TX, June 18–22, 2017. (paper) (slides) (poster)

• [C58] Soumi Chattopadhyay, Ansuman Banerjee, Bei Yu, “A Utility-Driven Data Transmission Optimization Strategy in Large Scale Cyber-Physical Systems”, IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE), pp. 1619–1622, Lausanne, Mar. 27–31, 2017. (paper)

• [C57] Hang Zhang, Fengyuan Zhu, Haocheng Li, Evangeline F. Y. Young, Bei Yu, “Bilinear Lithography Hotspot Detection”, ACM International Symposium on Physical Design (ISPD), pp. 7–14, Portland, OR, Mar. 19–22, 2017. (paper) (Best Paper Award)

• [C56] Jiaojiao Ou, Bei Yu, Xiaoqing Xu, Joydeep Mitra, Yibo Lin, David Z. Pan, “DSAR: DSA aware Routing with Simultaneous DSA Guiding Pattern and Double Patterning Assignment”, ACM International Symposium on Physical Design (ISPD), pp. 91–98, Portland, OR, Mar. 19–22, 2017. (paper) (slides)

• [C55] Haoyu Yang, Luyang Luo, Jing Su, Chenxi Lin, Bei Yu, “Imbalance Aware Lithography Hotspot Detection: A Deep Learning Approach”, SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 26–Mar. 2, 2017. (paper) (slides)

2016

• [J16] Tetsuaki Matsunawa, Bei Yu, David Z. Pan, “Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 15, no. 4, 043504, 2016. (paper)

• [J15] Bei Yu, Xiaoqing Xu, Subhendu Roy, Yibo Lin, Jiaojiao Ou, David Z. Pan, “Design for Manufacturability and Reliability in Extreme-Scaling VLSI”, Science China Information Sciences (SCIS), vol.59, June, 061406:2, 2016. (paper)

• [J14] Bei Yu, Kun Yuan, Jhih-Rong Gao, Shiyan Hu, David Z. Pan, “EBL Overlapping aware Stencil Planning for MCC System”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 21, no. 3, pp. 43:1–43:24, 2016. (paper)

• [J13] Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan, “PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning”, ACM Transactions on Design Automation of Electronic Systems (TODAES), vol. 21, no. 3, pp. 42:1–42:21, 2016. (paper)

• [J12] Tetsuaki Matsunawa, Bei Yu, David Z. Pan, “Optical Proximity Correction with Hierarchical Bayes Model”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 15, no. 2, 021009, 2016. (paper)

• [J11] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan, “Systematic Framework for Evaluating Standard Cell Middle-Of-Line (MOL) Robustness for Multiple Patterning Lithography”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 15, no. 2, 021202, 2016. (paper)

• [C54] Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu, “RippleFPGA: A Routability-Driven Placement for Large-Scale Heterogeneous FPGAs”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 67:1–67:8, Austin, TX, Nov. 7–10, 2016. (paper) (slides) (Invited Paper)

• [C53] Jian Kuang, Evangeline F. Y. Young, Bei Yu, “Incorporating Cut Redistribution with Mask Assignment to Enable 1D Gridded Design”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 48:1–48:8, Austin, TX, Nov. 7–10, 2016. (paper) (slides)

• [C52] Hang Zhang, Bei Yu, Evangeline F. Y. Young, “Enabling Online Learning in Lithography Hotspot Detection with Information-Theoretic Feature Optimization”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 47:1–47:8, Austin, TX, Nov. 7–10, 2016. (paper) (slides)

• [C51] Jin Miao, Meng Li, Subhendu Roy, Bei Yu, “LRR-DPUF: Learning Resilient and Reliable Digital Physical Unclonable Function”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 46:1–46:8, Austin, TX, Nov. 7–10, 2016. (paper) (slides)

• [C50] Meng Li, Kaveh Shamsi, Travis Meade, Zheng Zhao, Bei Yu, Yier Jin, David Z. Pan, “Provably Secure Camouflaging Strategy for IC Protection”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 28:1–28:8, Austin, TX, Nov. 7–10, 2016. (paper) (slides)

• [C49] Yibo Lin, Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Natarajan Viswanathan, Wen-Hao Liu, Zhuo Li, Charles J. Alpert, David Z. Pan, “MrDP: Multiple-row Detailed Placement of Heterogeneous-sized Cells for Advanced Nodes”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 7:1–7:8, Austin, TX, Nov. 7–10, 2016. (paper) (slides)

• [C48] Yibo Lin, Bei Yu, David Z. Pan, “Detailed Placement In Advanced Technology Nodes: A Survey”, IEEE International Conference on Solid -State and Integrated Circuit Technology (ICSICT), Hangzhou, Oct. 25–28, 2016. (paper) (Invited Paper)

• [C47] Hang Zhang, Haoyu Yang, Bei Yu, Evangeline F. Y. Young, “VLSI Layout Hotspot Detection Based on Discriminative Feature Extraction”, IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Jeju, Oct. 25–28, 2016. (Invited Paper)

• [C46] Derong Liu, Bei Yu, Salim Chowdhury, David Z. Pan, “Incremental Layer Assignment for Critical Path Timing”, ACM/IEEE Design Automation Conference (DAC), pp. 85:1–85:6, Austin, TX, June 5–9, 2016. (paper) (slides) (poster)

• [C45] Xiaotao Jia, Qiang Zhou, Yici Cai, Bei Yu, “MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router”, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 87–92, Boston, MA, May 18–20, 2016. (paper) (slides)

• [C44] Jiaojiao Ou, Bei Yu, David Z. Pan, “Concurrent Guiding Template Assignment and Redundant Via Insertion for DSA-MP Hybrid Lithography”, ACM International Symposium on Physical Design (ISPD), pp. 39–46, Sonoma, CA, April 3–6, 2016. (paper) (slides)

• [C43] Yibo Lin, Xiaoqing Xu, Bei Yu, Ross Baldick, David Z. Pan, “Triple/Quadruple Patterning Layout Decomposition via Novel Linear Programming and Iterative Rounding”, SPIE Intl. Symp. Advanced Lithography Conference, San Jose, CA, Feb. 21–25, 2016. (paper) (slides) (Best Student Paper Award)

• [C42] Tetsuaki Matsunawa, Bei Yu, David Z. Pan, “Laplacian Eigenmaps and Bayesian Clustering Based Layout Pattern Sampling and Its Applications to Hotspot Detection and OPC”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), pp. 679–684, Macau, Jan. 25–28, 2016. (paper) (slides)

• [C41] Yibo Lin, Bei Yu, Yi Zou, Zhuo Li, Charles J. Alpert, David Z. Pan, “Stitch Aware Detailed Placement for Multiple E-Beam Lithography”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), pp. 186–191, Macau, Jan. 25–28, 2016. (paper) (slides)

2015

• [J10] Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, David Z. Pan, “Directed Self-Assembly Cut Mask Assignment for 1D Design”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 14, no. 3, 031211, 2015. (paper)

• [J9] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan, “Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 5, pp. 699–712, 2015. (paper)

• [J8] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, Yibo Lin, Zhuo Li, Charles Alpert, David Z. Pan, “Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 5, pp. 726–739, 2015. (paper)

• [J7] Bei Yu, Kun Yuan, Duo Ding, David Z. Pan, “Layout Decomposition for Triple Patterning Lithography”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 34, no. 3, pp. 433–446, 2015. (paper)

• [J6] Bei Yu, Jhih-Rong Gao, Duo Ding, Xuan Zeng, David Z. Pan, “Accurate Lithography Hotspot Detection based on PCA-SVM Classifier with Hierarchical Data Clustering”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 14, no. 1, 011003, 2015. (paper)

• [J5] Bei Yu, Subhendu Roy, Jhih-Rong Gao, David Z. Pan, “Triple-patterning lithography (TPL) layout decomposition using end-cutting”, Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), vol. 14, no. 1, 011002, 2015. (paper)

• [C40] Bei Yu, Derong Liu, Salim Chowdhury, David Z. Pan, “TILA: Timing-Driven Incremental Layer Assignment”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 110–117, Austin, TX, Nov. 2–6, 2015. (paper) (slides)

• [C39] Yibo Lin, Bei Yu, Biying Xu, David Z. Pan, “Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 396–403, Austin, TX, Nov. 2–6, 2015. (paper) (slides)

• [C38] David Z. Pan, Lars Liebmann, Bei Yu, Xiaoqing Xu, Yibo Lin, “Pushing Multiple Patterning in Sub-10nm: Are We Ready?”, ACM/IEEE Design Automation Conference (DAC), pp. 197:1–197:6, San Francisco, CA, June 7–11, 2015. (paper) (Invited Paper)

• [C37] Xiaoqing Xu, Bei Yu, Jhih-Rong Gao, Che-Lun Hsu, David Z. Pan, “PARR: Pin Access Planning and Regular Routing for Self-Aligned Double Patterning”, ACM/IEEE Design Automation Conference (DAC), pp. 28:1–28:6, San Francisco, CA, June 7–11, 2015. (paper) (slides)

• [C36] Yibo Lin, Bei Yu, David Z. Pan, “High Performance Dummy Fill Insertion with Coupling and Uniformity Constraints”, ACM/IEEE Design Automation Conference (DAC), pp. 71:1–71:6, San Francisco, CA, June 7–11, 2015. (paper) (slides)

• [C35] Wei Ye, Bei Yu, Yong-Chan Ban, Lars Liebmann, David Z. Pan, “Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line”, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 289–294, Pittsburgh, PA, May 20–22, 2015. (paper) (slides)

• [C34] Jiaojiao Ou, Bei Yu, Jhih-Rong Gao, Moshe Preil, Azat Latypov, David Z. Pan, “Directed Self-Assembly Based Cut Mask Optimization for Unidirectional Design”, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 83–86, Pittsburgh, PA, May 20–22, 2015. (paper)

• [C33] Tetsuaki Matsunawa, Bei Yu, David Z. Pan, “Optical Proximity Correction with Hierarchical Bayes Model”, SPIE Intl. Symp. Advanced Lithography - Optical Microlithography XXVIII, San Jose, CA, Feb. 22–26, 2015. (paper) (slides)

• [C32] Tetsuaki Matsunawa, Jhih-Rong Gao, Bei Yu, David Z. Pan, “A New Lithography Hotspot Detection Framework Based on AdaBoost Classifier and Simplified Feature Extraction”, SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability IX, San Jose, CA, Feb. 22–26, 2015. (paper) (slides)

• [C31] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan, “A Systematic Framework for Evaluating Standard Cell Middle-Of-Line (MOL) Robustness for Multiple Patterning”, SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability IX, San Jose, CA, Feb. 22–26, 2015. (paper)

• [C30] Bei Yu, David Z. Pan, Tetsuaki Matsunawa, Xuan Zeng “Machine Learning and Pattern Matching in Physical Design”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), pp. 286–293, Japan, Jan. 19–22, 2015. (paper) (slides) (Invited Paper)

• [C29] Jiwoo Pak, Bei Yu, David Z. Pan, “Electromigration-aware Redundant Via Insertion”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), pp. 544–549, Japan, Jan. 19–22, 2015. (paper) (slides)

2014

• [C28] Bei Yu, Gilda Garreton, David Z. Pan, “Layout Compliance for Triple Patterning Lithography: An Iterative Approach”, SPIE/BACUS Photomask Symposium, Monterey, CA, Sept. 16–18, 2014. (paper) (slides) (Invited Paper)

• [C27] Bei Yu, David Z. Pan, “Layout Decomposition for Quadruple Patterning Lithography and Beyond”, SRC Techcon Conference, Austin, TX, Sept. 7–9, 2014. (paper)

• [C26] Jhih-Rong Gao, Xiaoqing Xu, Bei Yu, David Z. Pan, “MOSAIC: Mask Optimizing Solution With Process Window Aware Inverse Correction”, ACM/IEEE Design Automation Conference (DAC), pp. 52:1–52:6, San Francisco, CA, June 1–5, 2014. (paper) (slides) (Best Paper Award Nomination)

• [C25] Bei Yu, David Z. Pan, “Layout Decomposition for Quadruple Patterning Lithography and Beyond”, ACM/IEEE Design Automation Conference (DAC), pp. 53:1–53:6, San Francisco, CA, June 1–5, 2014. (paper) (slides) (poster)

• [C24] Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan, “Self-Aligned Double Patterning Aware Pin Access and Standard Cell Layout Co-Optimization”, ACM International Symposium on Physical Design (ISPD), pp. 101–108, Petaluma, CA, March 30–April 2, 2014. (paper)

• [C23] Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan, “Accurate Lithography Hotspot Detection Based on PCA-SVM Classifier with Hierarchical Data Clustering”, SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability VIII, San Jose, CA, Feb. 23–27, 2014. (paper)

• [C22] Bei Yu, Jhih-Rong Gao, Xiaoqing Xu, David Z. Pan, “Bridging the Gap from Mask to Physical Design for Multiple Patterning Lithography”, SPIE Intl. Symp. Advanced Lithography - Design-Process-Technology Co-optimization for Manufacturability VIII, San Jose, CA, Feb. 23–27, 2014. (paper) (Invited Paper)

• [C21] Jhih-Rong Gao, Bei Yu, David Z. Pan, “Self-aligned Double Patterning Layout Decomposition with Complementary E-Beam Lithography”, IEEE/ACM Asian and South Pacific Design Automation Conference (ASPDAC), pp. 143–148, Singapore, Jan. 20–23, 2014. (paper) (slides)

2013

• [J4] David Z. Pan, Bei Yu, Jhih-Rong Gao, “Design for Manufacturing with Emerging Nanolithography”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, no. 10, pp. 1453–1472, 2013. (paper) (Keynote Paper)

• [C20] Bei Yu, Xiaoqing Xu, Jhih-Rong Gao, David Z. Pan, “Methodology for Standard Cell Compliance and Detailed Placement for Triple Patterning Lithography”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 349–356, San Jose, CA, Nov. 18–21, 2013. (paper) (slides) (William J. McCalla Best Paper Award)

• [C19] Bei Yu, Yen-Hung Lin, Gerard Luk-Pat, Duo Ding, Kevin Lucas, David Z. Pan, “A High-Performance Triple Patterning Layout Decomposer with Balanced Density”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 163–169, San Jose, CA, Nov. 18–21, 2013. (paper) (slides)

• [C18] Jhih-Rong Gao, Bei Yu, Duo Ding, David Z. Pan, “Lithography Hotspot Detection and Mitigation in Nanometer VLSI”, IEEE International Conference on ASIC (ASICON), pp. 1–4, Shenzhen, China, Oct. 28–31, 2013. (paper) (Invited Paper)

• [C17] Bei Yu, Kun Yuan, Jhih-Rong Gao, David Z. Pan, “E-BLOW: E-Beam Lithography Overlapping aware Stencil Planning for MCC System”, ACM/IEEE Design Automation Conference (DAC), pp. 70:1–70:7, Austin, TX, June 2–6, 2013. (paper) (slides) (poster)

• [C16] Bei Yu, Jhih-Rong Gao, David Z. Pan, “Triple-Patterning Lithography (TPL) Layout Decomposition Using End-Cutting”, SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24–28, 2013. (paper) (slides)

• [C15] Jhih-Rong Gao, Bei Yu, Ru Huang, David Z. Pan, “Self-Aligned Double Patterning Friendly Configuration for Standard Cell Library Considering Placement”, SPIE Intl. Symp. Advanced Lithography, San Jose, CA, Feb. 24–28, 2013. (paper)

• [C14] Bei Yu, Jhih-Rong Gao, David Z. Pan, “L-Shape based Layout Fracturing for E-Beam Lithography”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 249–254, Japan, Jan. 22–25, 2013. (paper) (slides) (Best Paper Award Nomination)

2012

• [J3] Kun Yuan, Bei Yu, David Z. Pan, “E-Beam Lithography Stencil Planning and Optimization with Overlapped Characters”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 31, no. 2, pp. 167–179, Feb. 2012. (paper)

• [J2] Wei Zhong, Takeshi Yoshimura, Bei Yu, Song Chen, Sheqin Dong, Satoshi Goto, “Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E95-C, no. 4, pp. 535–545, 2012. (paper)

• [C13] Bei Yu, Jhih-Rong Gao, Duo Ding, Yongchan Ban, Jae-Seok Yang, Kun Yuan, Minsik Cho, David Z. Pan, “Dealing with IC Manufacturability in Extreme Scaling”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 240–242, San Jose, CA, Nov. 5–8, 2012. (paper) (Embedded Tutorial paper)

• [C12] Yen-Hung Lin, Bei Yu, David Z. Pan, Yih-Lang Li, “TRIAD: A Triple Patterning Lithography Aware Detailed Router”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 123–129, San Jose, CA, Nov. 5–8, 2012. (paper)

• [C11] David Z. Pan, Jhih-Rong Gao, Bei Yu, “VLSI CAD for Emerging Nanolithography”, International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1–4, 2012. (paper) (Invited paper)

• [C10] Kevin Lucas, Chris Cork, Bei Yu, Gerry Luk-Pat, Ben Painter, David Z. Pan, “Implications of Triple Patterning for 14 nm Node Design and Patterning”, SPIE Advanced Lithography Symposium Design for Manufacturability through Design-Process Integration VI (Conference 8327), Feb. 2012. (paper) (Keynote Paper)

• [C9] Duo Ding, Bei Yu, Joydeep Ghosh, David Z. Pan, “EPIC: Efficient Prediction of IC Manufacturing Hotspots With A Unified Meta-Classification Formulation”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 263–270, Sydney, Australia, Jan. 30–Feb. 3, 2012. (paper) (Best Paper Award)

• [C8] Duo Ding, Bei Yu, David Z. Pan, “GLOW: A Global Router for Low-Power Thermal-reliable Interconnect Synthesis using Photonic Wavelength Multiplexing”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 621–626, Sydney, Australia, Jan. 30–Feb. 3, 2012. (paper)

2011

• [C7] Bei Yu, Kun Yuan, Boyang Zhang, Duo Ding, David Z. Pan, “Triple Patterning Lithography Layout Decomposition”, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp. 1–8, San Jose, CA, Nov. 2011. (paper) (poster) (slides) (William J. McCalla Best Paper Award Nomination)

• [C6] Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto, “Network Flow-based Simultaneous Retiming and Slack Budgeting for Low Power Design”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 473–478, Japan, Jan. 2011. (paper) (slides)

• [C5] Wei Zhong, Bei Yu, Song Chen, Takeshi Yoshimura, Sheqin Dong, Satoshi Goto, “Application- Specific Network-on-Chip Synthesis: Cluster Generation and Network Component Insertion”, IEEE International Symposium on Quality Electronic Design (ISQED), pp. 144–149, Santa Clara, CA, March 14–16, 2011. (paper)

2010

• [C4] Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto, “Floorplanning and Topology Generation for Application-Specific Network-on-Chip”, IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC), pp. 535–540, Taipei, Jan. 2010. (paper) (slides)

• [C3] Tao Lin, Sheqin Dong, Bei Yu, Song Chen, Satoshi Goto, “A Revisit to Voltage Partitioning Problem”, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 115–118, Providence, RI, May 16–18, 2010. (paper)

2009

• [J1] Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto, “Voltage and Level-Shifter Assignment Driven Floorplanning”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E92-A, no. 12, Dec. 2009. (paper)

• [C2] Bei Yu, Sheqin Dong, Satoshi Goto, “Multi-Voltage and Level-Shifter Assignment Driven Floorplanning”, IEEE International Conference on ASIC (ASICON), pp. 1264–1267, Changsha, Oct. 20–23, 2009. (paper)

• [C1] Bei Yu, Sheqin Dong, Song Chen, Satoshi Goto, “Voltage-Island Driven Floorplanning Considering Level-Shifter Positions”, ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 51–56, Boston, MA, May 10–12, 2009. (paper)

Books / Book Chapters

[B2] Bei Yu, David Z. Pan, “Design for Manufacturability with Advanced Lithography”, Springer, 2016.

[B1] Bei Yu, David Z. Pan, “Layout Decomposition for Triple Patterning”, in Encyclopedia of Algorithms, M.-Y. Kao eds., Springer, 2015. (paper)

Dissertation

• [PHD] Bei Yu, “Design for Manufacturing with Advanced Lithography”, Ph.D. Dissertation at University of Texas at Austin, August 2014. (paper) (EDAA Outstanding Dissertation Award)

Newsletters

• [N3] Bei Yu, “Design for Manufacturability: From Ad Hoc Solution To Extreme Regular Design”, VLSI Circuits and Systems Letter, Volume 1, Issue 2, Oct. 2015. (pdf)

• [N2] Bei Yu, Gilda Garreton, David Z. Pan, “Layout Compliance for Triple Patterning Lithography: An Iterative Approach”, SPIE Newsroom.

• [N1] Kevin Lucas, Chris Cork, Bei Yu, David Pan, Gerry Luk-Pat, Alex Miloslavsky, Ben Painter, “Triple patterning in 10nm Node Metal Lithography”, SPIE Newsroom. (pdf)