Evangeline Young's Publications

To be updated soon ...
• Ripple: A Robust and Effective Routability-Driven Placer, Xu He, Tao Huang, Linfu Xiao, Haitong Tian and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 32(10):1546-1556, 2013.
• ObSteiner: An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees in the Presence of Complex Rectilinear Obstacles, Tao Huang and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 32(6):882-893, 2013.
• Postgrid Clock Routing for High Performance Microprocessor Designs, Haitong Tian, W.-C. Tang, Evangeline F.Y. Young and C. N. Sze, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 31(2):255-259, 2012.
• MSV-driven Floorplanning, Qiang Ma, Zaichen Qian, Evangeline F.Y. Young and Hai Zhou, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(8):1152-1162, 2011.
• Placement and Routing for Cross-Referencing Digital Microfluidic Biochips, Zigang Xiao and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(7):1000-1010, 2011.
• On the Construction of Optimal Obstacle-avoiding Rectilinear Steiner Minimum Tree, Liang Li, Tao Huang and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(5):718-731, 2011.
• Bus Matrix Synthesis based on Steiner Graphs for Power Efficient System-on-Chip Communications, R. Wang, Y. Zhang, N.C. Chou, Evangeline F.Y. Young, C.K. Cheng and R. Graham, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(2):167-179, 2011.
• Simultaneous Handling of Symmetry, Common Centroid and General Placement Constraints, Qiang Ma, Linfu Xiao, Yiu-cheong Tam and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 30(1):85-95, 2011.
• Complexity of 3-D Floorplans by Analysis on Graph Cuboidal Dual Hardness, Renshen Wang, Evangeline F.Y. Young and Chung-kuan Cheng, ACM Transaction on Design Automation of Electronic Systems, 15(4), Article 33, 2010.
• Multi-voltage Floorplan Design, Qiang Ma and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 29(4):607-617, 2010.
• Handling Routability in Floorplan Design with Twin Binary Trees , Steve T.W. Lai, Evangeline F.Y. Young and Chris C.N. Chu, Integration, the VLSI Journal. 42(4):449-456, 2009.
• Block Flipping and White Space Distribution for Wirelength Minimization , Chiu-Wing Sham and Evangeline F.Y. Young, Integration, the VLSI Journal, Vol. 42, No. 2, p246-253, February, 2009.
• Congestion Prediction in Early Stages of Physical Design , Chiu-Wing Sham, Evangeline F.Y. Young and Jingwei Lu, ACM Transaction on Design Automation of Electronic Systems, Vol. 14, No. 1, Article No. 12 (12:1-12:18), January, 2009.
• Multi-bend Bus Driven Floorplanning , Jill H.Y. Law and Evangeline F.Y. Young, Integration, the VLSI Journal, 41(2):306-316, 2008.
• Optimizing Wirelength and Routability by Searching Alternative Packings in Floorplanning , Chiu-Wing Sham, Evangeline F.Y. Young and Hai Zhou, ACM Transaction on Design Automation of Electronic Systems, Vol.13, No.1, Article No.21 (21:1-21:13), January, 2008.
• Wire Retiming Problem with Net Topology Optimization , Dennis K.Y. Tong, Evangeline F.Y. Young, Chris Chu and Sampath Dechu, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 26(9):1648-1660, 2007.
• Test Scheduling for BISTed Embedded SRAMs with Data Retention Faults , Qiang Xu, Baosheng Wang, Andre Ivanov and F. Y. Young, IEE Proceedings: Computers and Digital Techniques, Special Issue on ETS'06, Vol.1, pp.256-264, May 2007.
• Area Reduction by Deadspace Utilization on Interconnect Optimized Floorplan , Chiu-Wing Sham and Evangeline F. Y. Young, ACM Transaction on Design Automation of Electronic Systems, 12(1):1-11, 2007.
• Placement Constraints in Floorplan Design , Evangeline F.Y. Young, Chris C.N. Chu and M.L. Ho, IEEE Transactions on Very Large Scale Integration Systems, 12(7):745-745, 2004. (executables and data)
• Non-Rectangular Shaping and Sizing of Soft Modules for Floorplan Design Improvement , Chris C.N. Chu and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 23(1):71-79, 2004.
• Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning , Arthur W.K. Mak and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(7):952-959, 2003.
• Twin Binary Sequences: A Non-redundant Representation for General Non-slicing Floorplan , Evangeline F.Y. Young, Chris C.N. Chu and Zion Cien Shen, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(4):457-469, 2003.
• Routability Driven Floorplanning with Buffer Block Planning , C.W. Sham and Evangeline F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(4):470-480, 2003.
• Slicing Floorplan with Clustering Constraint , W.S. Yuen and F.Y. Young, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 22(5):654-658, 2003.
• Handling Soft Modules in General Nonslicing Floorplan using Lagrangian Relaxation , F.Y. Young, Chris C.N. Chu, W.S. Luk and Y.C. Wong, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 20(5):687-692, 2001.
• On Extending Slicing Floorplans to Handle L/T-shaped Modules and Abutment Constraints , F.Y. Young, Hannah H. Yang and D.F. Wong, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 20(6):800-807, 2001.
• Slicing Floorplan with Range Constraints , F.Y. Young, D.F. Wong and Hannah H. Yang, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 19(2):272-278, 2000.
• Slicing Floorplan with Boundary Constraints , F.Y. Young, D.F. Wong and Hannah H. Yang, IEEE Transactions of Computer-Aided Design of Integrated Circuits and Systems, 18(9), pp.1385-1389, 1999.
• Generation of Universal Series-Parallel Boolean Functions , F.Y. Young, C.N. Chu and D.F. Wong, Journal of the ACM, 46(3), pp.416-435, 1999.
• How Good are Slicing Floorplans , F.Y. Young and D.F. Wong, Integration, the VLSI Journal, Vol.23, pp.61-73, 1997.
• A Chinese Dictionary System Based on Fuzzy Logic and Object-Oriented Approach, K.S. Leung, Y. Fan and F.Y. Young, Computer Processing of Chinese and Oriental Languages - An International Journal of the Chinese Language Computer Society, World Scientific Publishing, Vol.6, No.2, pp.205-219, 1992, Canada.

• An Efficient Layout Decomposition Approach for Triple Patterning Lithography, Jian Kuang and Evangeline F.Y. Young, Proceedings ACM/IEEE Design Automation Conference, 2013.
• Ripple 2.0: High Quality Routability-Driven Placement via Global Router Integration, Xu He, Tao Huang, Wing-Kai Chow, Jian Kuang, Ka-Chun Lam, Wenzan Cai and Evangeline F.Y. Young, Proceedings ACM/IEEE Design Automation Conference, 2013.
• SRP: Simultaneous Routing and Placement for Congestion Refinement, Xu He, Wing-Kai Chow and Evangeline F.Y. Young, International Symposium on Physical Design, 2013.
• Construction of Rectilinear Steiner Minimum Trees with Slew Constraints over Obstacles, Tao Huang and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2012.
• Crosslink Insertion for Variation-Driven Clock Network Construction, Fuqiang Qian, Haitong Tian and Evangeline F.Y. Young, ACM Great Lakes Symposium on VLSI, 2012.
• Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement, Xu He, Tao Huang, Linfu Xiao, Haitong Tian, Guxin Cui and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2011.
• An Exact Algorithm for the Construction of Rectilinear Steiner Minimum Trees among Complex Obstacles, Tao Huang and Evangeline F. Y. Young, Proceedings ACM/IEEE Design Automation Conference, 2011.
• An Optimal Algorithm for Layer Assignment of Bus Escape Routing on PCBs, Qiang Ma, Evangeline F. Y. Young and Martin D. F. Wong, Proceedings ACM/IEEE Design Automation Conference, 2011.
• Grid-to-Ports Clock Routing for High Performance Microprocessor Designs, Haitong Tian, Wai-Chung Tang, Evangeline F.Y. Young and C. N. Sze, International Symposium on Physical Design, 2011. Best Paper Award Nomination.
• A Monte-Carlo Floating-Point Unit for Self-Validated Arithmetic, Jackson Ho-Chuen Yeung, Evangeline F. Y. Young and Philip Leong, Proceedings ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2011.
• A Provably Good Approximation Algorithm for Rectangle Escape Problem with Application to PCB Routing, Qiang Ma, Hui Kong, Martin D. F. Wong and Evangeline F. Y. Young, Proceedings IEEE Asia South Pacific Design Automation Conference, 2011.
• Obstacle-avoiding Rectilinear Steiner Minimum Tree Construction: An Optimal Approach, Tao Huang and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2010. Best Paper Award Nomination.
• Practical Placement and Routing Techniques for Analog Circuit Designs, Linfu Xiao, Evangeline F.Y. Young, Xiaoyong He and K.P. Pun, Proceedings IEEE International Conference on Computer-Aided Design, 2010.
• Local Clock Skew Minimization Using Blockage-aware Mixed Tree-Mesh Clock Network, Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, Tao Huang, Haitong Tian and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2010.
• Droplet-routing-aware Module Placement for Cross-referencing Biochips, Zigang Xiao and Evangeline F.Y. Young, International Symposium on Physical Design, 2010.
• Physical Synthesis of Bus Matrix for High Bandwidth Low Power On-chip Communications, Renshen Wang, Evangeline F.Y. Young, Ronald Graham and Chung-Kuan Cheng, International Symposium on Physical Design, 2010.
• A Dual-MST Approach for Clock Network Synthesis, Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham and Evangeline F.Y. Young, Proceedings IEEE Asia South Pacific Design Automation Conference, 2010. Best Paper Award Nomination (13 out of 340).
• CrossRouter: A Droplet Router for Cross-Referencing Digital Microfluidic Biochips, Zigang Xiao and Evangeline F.Y. Young, Proceedings IEEE Asia South Pacific Design Automation Conference, 2010. (executables and data)
• Fixed-outline Thermal-aware 3D Floorplanning, Linfu Xiao, Subarna Sinha, Jingyu Xu and Evangeline F.Y. Young, Proceedings IEEE Asia South Pacific Design Automation Conference, 2010.
• Generation of Optimal Obstacle-avoiding Rectilinear Steiner Minimum Tree, Liang Li, Zaichen Qian and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2009
• Multi-voltage Floorplan Design with Optimal Voltage Assignment, Zaichen Qian and Evangeline F.Y. Young, International Symposium on Physical Design, 2009.
• Analog Placement with Common Centroid and 1-D Symmetry Constraints, Linfu Xiao and Evangeline F.Y. Young, Proceedings IEEE Asia South Pacific Design Automation Conference, 2009. Best Paper Award Nomination (14 out of 355).
• Obstacle-avoiding Rectilinear Steiner Tree Construction, Liang Li and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2008.
• Network Flow Based Power Optimization under Timing Constraints in MSV-driven Floorplanning, Qiang Ma and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2008. (executables and data)
• 3-D Floorplanning using Labeled Tree and Dual Sequences , Renshen Wang, Evangeline F.Y. Young, Yi Zhu, Fan Chung Graham, Ronald Graham and Chung-Kuan Cheng, International Symposium on Physical Design, 2008.
• TCG-based Bus Driven Floorplanning, Tilen Ma and Evangeline F.Y. Young, Proceedings IEEE Asia South Pacific Design Automation Conference, 2008.
• Voltage Island-Driven Floorplanning, Qiang Ma and Evangeline F.Y. Young, Proceedings IEEE International Conference on Computer-Aided Design, 2007. (executables and data)
• Analog Placement with Common Centroid Constraints, Qiang Ma, Evangeline F.Y. Young and K.P. Pun, Proceedings IEEE International Conference on Computer-Aided Design, 2007. ( executables and data - This version handles common centroid, symmetry and other general placement constraints.)
• Post-placement Voltage Island Generation, Royce L.S. Ching, Evangeline F.Y. Young, Kevin C.K. Leung and Chris Chu, Proceedings IEEE International Conference on Computer-Aided Design, 2006.
• Analog Placement with Symmetry and Other Placement Constraints, Yiu-cheong Tam, Evangeline F.Y. Young and Chris Chu, Proceedings IEEE International Conference on Computer-Aided Design, 2006. (executables and data)
• Optimal Cell Flipping in Placement and Floorplanning, Chiu-wing Sham, Evangeline F.Y. Young and Chris Chu, Proceedings ACM/IEEE Design Automation Conference, 2006.
• Retention-Aware Test Scheduling for BISTed Embedded SRAMs, Qiang Xu, Baosheng Wang and Evangeline F.Y. Young, IEEE European Test Symposium, pp.83-88, 2006.
• Block Alignment in 3D Floorplan using Layered TCG, Jill H.Y. Law, Evangeline F.Y. Young and Royce L.S. Ching, ACM Great Lakes Symposium on VLSI, pp.376-380, 2006.
• Shuttle Mask Floorplanning with Modified Alpha-Restricted Grid, Royce L.S. Ching and Evangeline F.Y. Young, ACM Great Lakes Symposium on VLSI, pp.85-90, 2006. (executables and data)
• Multi-Bend Bus Driven Floorplanning, Jill H.Y. Law and Evangeline F.Y. Young, International Symposium on Physical Design, pp.113-120, 2005.
• Congestion Prediction in Early Stages, Chiu-wing Sham and Evangeline F.Y. Young, International Workshop on System-Level Interconnect Prediction, pp.91-98, 2005.
• Congestion Prediction in Floorplanning, Chiu-wing Sham and Evangeline F.Y. Young, IEEE Asia South Pacific Design Automation Conference, pp.1107-1110, 2005.
• Multilevel Interconnect-Driven Floorplanning, Evangeline F.Y. Young and Joseph C.S. Lau, Mid-West Symposium on Circuits and Systems, pp., 2005.
• Area Reduction on Interconnect Optimized Floorplan using Deadspace Utilization, Chiu-wing Sham and Evangeline F.Y. Young, Mid-West Symposium on Circuits and Systems, pp., 2005.
• Performance-Driven Register Insertion in Placement, Dennis K.Y. Tong and Evangeline F.Y. Young, International Symposium on Physical Design, pp.53-60, 2004.
• Retiming with Interconnect and Gate Delay, Chris C.N. Chu, Evangeline F.Y. Young, Dennis K.Y. Tong and Sampath Dechu, Proceedings IEEE International Conference on Computer-Aided Design, pp.221-226, 2003. (executables and data)
• Clustering Based Acyclic Multi-way Partitioning, Eric S.H. Wong, Evangeline F.Y. Young and W.K. Mak, Proceedings of the 13th ACM Great Lakes Symposium on VLSI, pp.203-206, 2003.
• A New and Efficient Congestion Evaluation Model in Floorplanning: Wire Density Control with Twin Binary Trees, Steve T.W. Lai, Evangeline F.Y. Young and Chris C.N. Chu, Proceedings of Design, Automation and Test in Europe, 2003.
• Fast Buffer Planning and Congestion Optimization in Interconnect-driven Floorplanning, Keith K.C. Wong and Evangeline F.Y. Young, IEEE Asia South Pacific Design Automation Conference, pp.411-416, 2003. Best Paper Award Nomination.
• Interconnect-Driven Floorplanning by Searching Alternative Packings, Bruce C.W. Sham, Evangeline F.Y. Young and Hai Zhou, IEEE Asia South Pacific Design Automation Conference, pp.417-422, 2003.
• Twin Binary Sequences: A Non-redundant Representation for General Non-slicing Floorplan, Evangeline F.Y. Young, Chris C.N. Chu and Zion Cien Shen, International Symposium on Physical Design, pp.196-201, 2002.
• Routability Driven Floorplanner with Buffer Block Planning, C.W. Sham and Evangeline F.Y. Young, International Symposium on Physical Design, pp.50-55, 2002.
• Temporal Logic Replication for Dynamically Reconfigurable FPGA Partitioning, Wai-Kei Mak and Evangeline F.Y. Young, International Symposium on Physical Design, pp.190-195, 2002.
• Congestion Estimation with Buffer Planning in Floorplan Design, C.W. Sham, W.C. Wong and Evangeline F.Y. Young, Proceedings of Design, Automation and Test in Europe, pp.696-701, 2002.
• Non-rectangular Shaping and Sizing of Soft Modules in Floorplan Design, Chris C.N. Chu and Evangeline F.Y. Young, Proceedings of Design, Automation and Test in Europe, pp.1101, 2002.
• A Unified Method to Handle All Kinds of Placement Constraints in General Non-slicing Floorplan , F.Y. Young, Chris C.N. Chu and M.L. Ho, IEEE Asia South Pacific Design Automation Conference, pp.661-667, 2002. (executables and data)
• Slicing Floorplans with Clustering Constraints , W.S. Yuen and F.Y. Young, IEEE Asia South Pacific Design Automation Conference, pp.503-508, 2001.
• On Extending Slicing Floorplans to Handle L/T-shaped Modules and Abutment Constraints , F.Y. Young, Hannah H. Yang and D.F. Wong, Conference on Chip Design Automation, 16th World Computer Congress, August, 2000, pp.269-276.
• Floorplan Area Minimization using Lagrangian Relaxation , F.Y. Young, Chris C.N. Chu, W.S. Luk and Y.C. Wong, International Symposium on Physical Design, pp.174-179, 2000.
• Integrated Floorplanning and Interconnect Planning , H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, Hannah H. Yang and Naveed Sherwani, Proceedings IEEE International Conference on Computer-Aided Design, pp.354-357, 1999.
• Slicing Floorplans with Range Constraints , F.Y. Young and D.F. Wong, International Symposium on Physical Design, pp.97-102, 1999.
• Slicing Floorplans with Boundary Constraints , F.Y. Young and D.F. Wong, IEEE Asia South Pacific Design Automation Conference, pp. 17-20, 1999.
• Slicing Floorplans with Pre-placed Modules , F.Y. Young and D.F. Wong, Proceedings IEEE International Conference on Computer-Aided Design, pp.252-258, 1998.
• How Good are Slicing Floorplans? , F.Y. Young and D.F. Wong, International Symposium on Physical Design, pp.144-149, 1997.
• On the Construction of Universal Series-Parallel Functions for Logic Module Design , F.Y. Young and D.F. Wong, IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp.482-488, 1997.
• Parallel implementation of partially connected recurrent network, F.Y. Young and L.W. Chan, IEEE Conference on Neural Networks, Orlando, Vol.4, pp.2058-2063, 1994.
• Chaos in recurrent networks, L.W. Chan and F.Y.Young, International Symposium on Speech, Image Processing and Neural Networks, Hong Kong, Vol.1, pp.225-229, 1994.
• Using recurrent network for time series prediction, Lai wan Chan and F.Y. Young, World Congress on Neural Networks, Portland, Vol.4, pp.332-336, 1993.
• Ring-structured recurrent neural network, Lai wan Chan and F.Y. Young, World Congress on Neural Networks, Portland, Vol.4, pp.328-331, 1993.
• Sequence recognition using recurrent backpropagation network, F.Y. Young and L.W. Chan, Proceedings of The International Joint Conference on Neural Networks, Beijing, China, Vol.2, pp.557-562, 1992.

• On the Construction of Universal Series-Parallel Functions for Logic Module Design, F.Y. Young and D.F. Wong, TR-97-13, Department of Computer Sciences, The University of Texas at Austin, April 1997.
• Locally connected recurrent networks, L. W. Chan and Evan Fung-Yu YOUNG, The Chinese University of Hong Kong, 1995.