B.Sc. (CUHK), Ph.D. (UT Austin)
Chairman and Professor of Department of Computer Science & Engineering
Fellow of IEEE, Distinguished Member of ACM
- Associate Editor ACM Transactions on Design Automation of Electronic Systems
- Associate Editor Integration, the VLSI Journal
Biography
Evangeline Young received her B.Sc. and M.Phil. degree in Computer Science from The Chinese University of Hong Kong and received her Ph.D. degree from The University of Texas at Austin. BTW, she accepted Jesus on Oct 20, 1996. She joined the Department of Computer Science and Engineering in the Chinese University of Hong Kong as an assistant professor and is now a professor in the same department. Her research interests include CAD of VLSI circuits, algorithms, combinatorial optimization and AI. She has served in the program committees of DAC, ICCAD, ASP-DAC, ISPD, GLSVLSI, DATE and the editorial boards of IEEE TCAD, ACM TODAES and Integration, the VLSI Journal. She also served in the executive committee of ISPD and ICCAD. Her research group has won championships and prizes in renown EDA contests, including the 2018-20, 2015-16, 2012-13, CAD Contests at ICCAD, DAC 2012, and ISPD 2015-20 and 2010-11.
- X. He, T. Huang, L. Xiao, H. Tian, G. Cui, Evangeline F.Y. Young: Ripple: An Effective Routability-Driven Placer by Iterative Cell Movement. ICCAD 2011: 74-79
- Evangeline F.Y. Young, Chris C.N. Chu, Z.C. Shen: Twin Binary Sequences: a Nonredundant Representation for General Non-Slicing Floorplan. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 457-469, 2003
- H.M. Chen, Martin D.F. Wong, H. Zhou, Evangeline F.Y. Young, H.H. Yang, N. Sherwani: Integrated Floorplanning and Interconnect Planning. Layout Optimization in VLSI Design, 1-18
- J. Kuang, Evangeline F. Y. Young: An Efficient Layout Decomposition Approach for Triple Patterning Lithography. DAC 2013: 69:1-69:6
- G. Chen, Evangeline F.Y. Young: SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1217-1230 (2020)
- G. Chen, C.-W. Pui, H. Li, Evangeline F. Y. Young: Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1902-1915 (2020)
- J. Liu, C.-W. Pui, F. Wang, Evangeline F. Y. Young: CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model. DAC 2020: 1-6
- B. Jiang, J. Chen, J. Liu, L. Liu, F. Wang, X. Zhang, Evangeline F.Y. Young: CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel Sizing. ICCAD 2020: 1-9
- B. Jiang, L. Liu, Y. Ma, H. Zhang, B. Yu, Evangeline F.Y. Young: Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimization. ICCAD 2020: 1-9
- Champion, 2020 CAD Contest at ICCAD on Routing with Cell Movement
- Champion, 2020 ISPD Wafer-Scale Deep Learning Accelerator Placement
- Best Paper Award, IEEE/ACM William J. Mccalla International Conference on Computer-Aided Design, 2017
- Best Paper Award, ACM International Symposium on Physical Design, 2017
- Vice Chancellor’s Exemplary Teaching Award, CUHK (2001-02)