Qiang Xu

Department of Computer Science & Engineering
The Chinese University of Hong Kong
Shatin, N.T., Hong Kong                  

Email:
Phone:
Fax: 
Office: 

qxu AT cse.cuhk.edu.hk
+852.3943.8436
+852.2603.5024
Room 1008, Ho Sin Hang Building 

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Research@CURE

Teaching

Publications

Professional Activities

Vacancy

Research Objectives

The relentless scaling of CMOS technology has brought with it enhanced functionality and improved performance at lower cost per silicon unit area in every new generation. At the same time, the emerging new types of failure mechanisms, the increasing design complexity and the stringent time-to-market pressure lead to more circuit failures. The research objective of the CURE laboratory  is to address the many challenging issues in designing and testing the next generation of VLSI circuits, including (i) reliable and fault-tolerant computing, (ii) manufacturing test in the nanometer era; and (iii) post-silicon validation and silicon debug.

Research Sponsors:

  HK Research Grant Council (RGC)

  HK Innovation and Technology Fund (ITF)

  National 863 Plan

  National Natural Science Foundation of China (NSFC)

Research Group

• Feng YUAN

• Jie ZHANG

• Zelong SUN

• Qian ZHANG

• Ting WANG

• Yannan Liu

• Lingxiao Wei

Graduated Students

• Yubin ZHANG (First position: Shenzhen Institutes of Advanced Technology, CAS)

• Lin HUANG (First position: Ph.D. student, Stanford University)

• Xiao LIU (First position: Postdoc, UC Berkeley)

• Haile YU (First position: ClusterTech)

• Yuxi LIU (First position: Kaiyuan Securities)

• Feng YUAN (First position: Postdoc, CUHK)

• Li JIANG (First position: Assistant Professor, Shanghai Jiao Tong University)

• Rong YE (First position: Postdoc, Imperial College)

On-Going Research Projects

•  Design and Verification for Hardware Security

•  Design and Test for Timing Speculation

•  Yield Enhancement for 3D-Stacked Integrated Circuits

•  Automated Tracing in Post-Silicon Validation

•  Fault-Tolerant and Variation-Tolerant High-Performance Manycore Processors

Completed Projects

•  Aging-Aware SoC Design 

•  Low-Power Testing

•  Multi-Core Debug Platform for NoC-Based Systems

•  SoC Test Architecture Design and Optimization for Signal Integrity Faults

•  Testing NoC-Based Systems

Research Collaborators

• Krishnendu Chakrabarty, Duke University

• Andre Ivanov, University of British Columbia

• Baosheng Wang, AMD

• Xiaowei Li, Yinhe Han, Chinese Academy of Sciences

• Dong Xiang, Tsinghua University