SoC Test Architecture Design and Optimization for Signal Integrity Faults

Principle Investigator: Qiang Xu

Graduate Students: Yubin Zhang; Feng Yuan



Project Summary


With the ever shrinking feature size of very large scale integration (VLSI) technology and the increasing operational frequency of high-performance system-on-a-chip (SOC) design, cross-coupling effects among the interconnects between embedded cores can be strong enough to distort the signal waveform significantly and cause the design to malfunction. As a result, signal integrity (SI), the ability of a signal to generate correct responses in a circuit, has become a major concern for the core-external interconnects in SOCs today. Since it is unacceptable to over-design the circuit to solve the SI-related problems and it is impossible to predict the occurrence of defects that aggravate the coupling effects among interconnects, manufacturing test strategies are essential to be developed to detect these SI faults. On the one hand, various SI fault models and the associated test methodologies have been proposed in the literature, but none of them is both effective in terms of physical defect coverage and efficient in terms of testing time. On the other hand, most prior work in modular SOC test architecture design and optimization focuses on core internal testing only, without considering the ever-important core external interconnect SI faults. As the test cost for the interconnect SI faults can be comparable to or even higher than the test cost for the core internal logic, it is necessary to investigate new design and optimization techniques for SOC test architecture to reduce the overall SOC test cost for both core internal logic and core external interconnects.


The research directions include core test wrapper design, distributed hierarchical test controller design, test set compaction strategies, and effective and efficient test scheduling algorithms for SOCs with interconnect SI faults.

Papers and Presentations

SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects, Proc. IEEE International Test Conference (ITC), Oct. 2008.

  • Paper
  • Presentation (coming soon)

Test-Wrapper Designs for the Detection of Signal-Integrity Faults on Core-External Interconnects of SoCs, IEEE International Test Conference (ITC), Oct. 2007.

SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects, ACM/IEEE Design Automation Conference (DAC), June 2007.