Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification. One effective silicon debug technique is to monitor and trace the behaviors of the circuit during its normal operation. However, designers can only afford to tap a small portion of internal signals in the design due to the associated overhead (typically in the thousand range for million-gate designs). Selecting which signals to tap is therefore a crucial issue for the effectiveness of this technique. At the same time, with a given number of tapped signals, only a subset of them (say, 32 signals) can be selected to be observed in each debug process due to the trace bandwidth limit. These trace signals need to be transferred to on-chip buffers and/or off-chip trace ports for analysis.

In current practice, designers manually select those signals that are considered to be vulnerable to bugs or important for analysis to trace, based on their design experience. While their knowledge about the design is of great help in trace signal selection, this ad-hoc process cannot guarantee the quality of the selected trace signals. More importantly, bugs often occur in unexpected scenarios and it is impossible to predict which signals will be related to them during the design phase. From this aspect, to achieve effective bug identification, we should at least add some trace signals that are selected in an automated manner without designers' intervention.