Automated Signal Tracing in Post-Silicon Validation

Principle Investigators: Qiang Xu

Graduate Student: Xiao Liu



Project Summary


Today's complex integrated circuit designs increasingly rely on post-silicon validation to eliminate bugs that escape from pre-silicon verification. One effective silicon debug technique is to monitor and trace the behaviors of the circuit during its normal operation. However, designers can only afford to tap a small portion of internal signals in the design due to the associated overhead (typically in the thousand range for million-gate designs). Selecting which signals to tap is therefore a crucial issue for the effectiveness of this technique. At the same time, with a given number of tapped signals, only a subset of them (say, 32 signals) can be selected to be observed in each debug process due to the trace bandwidth limit. These trace signals need to be transferred to on-chip buffers and/or off-chip trace ports for analysis.

In current practice, designers manually select those signals that are considered to be vulnerable to bugs or important for analysis to trace, based on their design experience. While their knowledge about the design is of great help in trace signal selection, this ad-hoc process cannot guarantee the quality of the selected trace signals. More importantly, bugs often occur in unexpected scenarios and it is impossible to predict which signals will be related to them during the design phase. From this aspect, to achieve effective bug identification, we should at least add some trace signals that are selected in an automated manner without designers' intervention.


While we cannot afford to trace a large number of signals at the same time, it is possible to expand the logic states on the few trace signals to restore many missing states on those untraced signals, according to the circuit's logic structures. In this project, we plan to define the above gate-level restorabilities for visibility enhancement in a theoretically-precise manner and propose novel automated tap signal selection algorithms that are able to restore a large number of missing states.

Papers and Presentations

"On Multiplexed Signal Tracing for Silicon Debug", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1-6, March 2011.

"On Signal Tracing for Debugging Speedpath-Related Electrical Errors in Post-Silicon Validation", Proc. IEEE Asian Test Symposium (ATS), pp. 243-248, Dec. 2010.

"On Signal Tracing in Post-Silicon Validation", Proc. IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 262-267, Jan. 2010.  (invited paper)

"Interconnection Fabric Design for Tracing Signals in Post-Silicon Validation", Proc. ACM/IEEE Design Automation Conference (DAC), pp. 352-357, July 2009.  (acceptance rate: 148/682 = 21.7%)

"Trace Signal Selection for Visibility Enhancement in Post-Silicon Validation", Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pp. 1338-1343, Apr. 2009.  (acceptance rate: 226/965 = 23.4%)