Low Power Testing
Principle Investigator: Qiang Xu
Graduate Students: Xiao Liu; Jia Li (ICT, CAS); Dianwei Hu (Tsinghua)
One of the major concerns in seeking a reliable test strategy for todayís very large scale integration (VLSI) integrated circuit (IC) is that, an ICís power dissipation during testing can be significantly higher than that during normal operation. This brings the following problems: (i) the accumulated effect of test power dissipation can generate elevated test heat that requires more expensive package or causes permanent damage to the circuit under test (CUT); (ii) the excessive instantaneous test power dissipation can result in large voltage drop that causes circuit to malfunction in test mode only and thus lead to yield loss. Therefore, reducing power consumption has become an important objective of todayís test development process.
We take two approaches in reducing test power: (1). a novel low-power virtual test partitioning technique. The basic idea is to partition the circuit in such way that the faults in the glue logic between subcircuits can be detected by patterns with low power dissipation that are applied at the entire circuit level, while the patterns with high power dissipation can be applied within a partitioned subcircuit without loss of fault coverage. Scan chain routing cost has also been considered during the partitioning process. (2). an impact-oriented X-filling technique, namely iFill. The abasic idea is to fill as few as possible X-bits with higher impact to keep the capture-power under the peak power limit of the CUT, and use all the remaining X-bits to reduce shift-power as much as possible to cut down the CUTís average power consumption. In addition, different from prior work on shift-power reduction that considers the power consumption during shift-in process only, which, unfortunately, may lead to excessive power for the shift-out process. The proposed iFill technique is able to cut down power consumptions in both shift-in and shift-out processes, thus leading to much higher shift-power reduction.
Papers and Presentations
A Generic Framework for Scan Capture Power Reduction in Fixed-Length Symbol-based Test Compression Environment, accepted for publication in Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), Apr. 2009.
On Capture Power-Aware Test Data Compression for Scan-Based Testing, IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2008.
State-Sensitive X-Filling Scheme for Scan Capture Power Reduction, IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, July 2008.
iFill: An Impact-Oriented X-Filling Method for Shift- and Capture-Power Reduction in At-Speed Scan-Based Testing, IEEE/ACM Design, Automation, and Test in Europe (DATE), March 2008.
On Reducing Both Shift and Capture Power for Scan-Based Testing, IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC) , Jan. 2008.
Pattern-Directed Circuit Virtual Partitioning for Test Power Reduction, IEEE International Test Conference (ITC), Oct. 2007.