Testing NoC-Based Systems: Is NoC a Cost-Effective Test Access Mechanism?

Principle Investigator: Qiang Xu

Graduate Students: Feng Yuan; Lin Huang




Project Summary


Existing work on testing NoC-based systems advocates to reuse the on-chip network itself as test access mechanism (TAM) to transport test data to/from embedded cores. While this methodology obviously reduces the routing cost when compared to the case that dedicated test buses are introduced as TAMs, it is not clear whether it is beneficial in terms of other important factors that significantly affect test cost, e.g., testing time, test control complexity and test reliability. In this project, we plan to re-examine the issue of using NoC as TAM in order to facilitate designers to construct a cost-effective system test architecture based on their requirements.


In this project, we re-examine the reuse of NoC as TAM and conduct comprehensive comparison for the case with NoC itself as TAM (denoted as NoC-TAM) and the case with dedicated test buses as TAM (denoted as DTB-TAM), when testing NoC-based systems. The main difference of the two test strategies lies in the fact that test data are transferred through on-chip network in functional mode in NoC-TAM scheme and hence are constrained by the NoC working mechanism (e.g., routing scheme and error control mechanisms); while for the DTB-TAM scheme, however, designers have full controllability on how to transfer test data to the CUTs. In terms of testing time, instead of presenting new NoC-TAM optimization algorithms to compare with existing DTB-TAM solutions, we derive its theoretical lower bound and compare with the ones for DTB-TAM presented in. In addition, we also compare the two test strategies in terms of other test cost factors, e.g., DFT area, test control complexity and test reliability.

 Papers and Presentations

Re-Examining the Use of Network-on-Chip as Test Access Mechanism, IEEE/ACM Design, Automation, and Test in Europe (DATE), March 2008.

  • Paper

  • Presentation (coming soon)

On Reliable Modular Testing with Vulnerable Test Access Mechanisms, ACM/IEEE Design Automation Conference (DAC), June 2008.

  • Paper

  • Presentation (coming soon)