CENG5030 Energy Efficient Computing – Spring 2019

Lecture:	M 10:30-12:15	Venue: BMS 2
	T 09:30-10:15	Venue: ERB 408
Tutorial	T 10:30-11:15
Course Instructor:	Prof. Bei Yu	byu@cse.cuhk.edu.hk
Course Tutors:	Yuzhe Ma	yzma@cse.cuhk.edu.hk

• Honesty in Academic Work

• Staff Student Expectations

Announcements

Description

This course provides an introduction to low power computing, covering both classical topics (Part I) and emerging topics (Part II). Part I discusses energy efficiency computing at both architecture and circuit level; while Part II covers energy efficient computing in Deep Neural Networks (DNNs).

Course Requirements

• This course uses a seminar, not a lecture, format. Each lecture covers particular topics from assigned papers. Students are expected to read the assigned papers and to prepare for course discussions.

• Part-1 Report: A mini research proposal on the topic of energy efficiency, consisting of literature survey, motivation, and description of technical idea. The report is judged by completeness of survey, clearness of motivation, and novelty of the idea.

• Part-2 Report: On the topic of DNN compression or speed-up. The report is judged by the novelty of ideas as well as the significance of empirical results. (project description)

• Grading: Class Participation (30%), Part-1 Report (20%), Part-1 Presentation (15%), Part-2 Report (20%), Part-2 Presentation (15%).

Schedule

Week	Date	Topic	Remark
1	Jan. 07	P1-1 Introduction (slides)
	Jan. 08	P1-2 Voltage Scaling (slides)	9:30-11:15
2	Jan. 14	continue on voltage scaling
	Jan. 15	continue on voltage scaling	9:30-11:15
3	Jan. 21	n/a	Instructor in travel
	Jan. 22	n/a	Instructor in travel
4	Jan. 28	P1-3 DVFS (slides)
	Jan. 29	P1-4 Switching Activity (slides)	9:30-11:15
5	Feb. 04	n/a	Lunar New Year Holiday
	Feb. 05	n/a	Lunar New Year Holiday
6	Feb. 11	P1-5 Approximate Computing (slides)
	Feb. 12	continue on approximate computing	9:30-11:15
7	Feb. 18	Part-1 Presentations
	Feb. 19	Part-1 Presentations	9:30-11:15
8	Feb. 25	Part-1 Presentations
	Feb. 26	n/a
9	Mar. 04	P2-1 Introduction (slides)
	Mar. 05	Tutorial on Caffe (slides)	9:30-11:15
10	Mar. 11	P2-2 Accurate Speedup (slides)
	Mar. 12	P2-3 Inaccurate Speedup-1 (slides)	9:30-11:15
11	Mar. 18	n/a	Instructor in travel
	Mar. 19	n/a	Instructor in travel
12	Mar. 25	P2-4 Inaccurate Speedup-2 (slides)
	Mar. 26	P2-5 Inaccurate Speedup-3 (slides)	9:30-11:15
13	Apr. 01	n/a	Reading Week
	Apr. 02	n/a	Reading Week
14	Apr. 08	n/a
	Apr. 09	P2-6 NAS (slides)
15	Apr. 15	Part-2 Presentations	10:30-12:45
	Apr. 16	Part-2 Presentations	9:30-11:45

Important Dates

• 23:59pm, Feb. 09, 2019: Part-1 report abstract deadline.

• 23:59pm, Feb. 17, 2019: Part-1 report final deadline.

• 23:59pm, Apr. 28, 2019: Part-2 report final deadline.

• Presentation 1 Schedule:

  

• Presentation 2 Schedule:

  

References

• Stefanos Kaxiras, Margaret Martonosi, “Computer Architecture Techniques for Power-Efficiency”, 2008.

• Jan Rabaey, “Low Power Design Essentials”, 2009.

P1-1:

• Mudge, Trevor, “Power: A first-class architectural design constraint”, Computer 2001.

P1-2:

• Wan-Ping Lee, Hung-Yi Liu, and Yao-Wen Chang, “Voltage island aware floorplanning for power and timing optimization”, ICCAD 2006.

• Qiang Ma, and Evangeline FY Young, “Voltage island-driven floorplanning”, ICCAD 2007.

• Hung-Yi Liu, Wan-Ping Lee, and Yao-Wen Chang, “A provably good approximation algorithm for power optimization using multiple supply voltages”, DAC 2007.

P1-3:

• Frances Yao, Alan Demers, and Scott Shenker, “A scheduling model for reduced CPU energy”, FOCS 1995.

• Mark Weiser et al., “Scheduling for reduced CPU energy”, OSDI 1994.

• Chung-Hsing Hsu and Ulrich Kremer, “The design, implementation, and evaluation of a compiler algorithm for CPU energy reduction”, PLDI 2003.

• Dan Ernst et al., “Razor: A low-power pipeline based on circuit-level timing speculation”, MICRO 2003.

P1-4:

• Hai Li, Swarup Bhunia, Yiran Chen, Kaushik Roy, T. N. Vijaykumar, “DCG: deterministic clock-gating for low-power microprocessor design”, TVLSI 2004.

• David Brooks and Margaret Martonosi, “Dynamically exploiting narrow width operands to improve processor power and performance”, HPCA 1999.

• David H. Albonesi, “Selective cache ways: On-demand cache resource allocation”, MICRO 1999.

P1-5:

• Qiang Xu, Todd Mytkowicz, and Nam Sung Kim. “Approximate computing: A survey”, MDAT 2016.

P2:

• Erwei Wang et al., “Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going”, CSUR, 2019.