Clock Network Synthesis

Clock network construction is one of the most important research topics in both the industrial and academic communities. Among the possible objectives including power, signal slew, nominal skew and wire length, clock skew is a crucial one that limits the performance of a synchronous digital system. It directly relates to the maximum frequency of the circuit. On the other hand, the effect of process variation is becoming more significant and the unwanted clock skew caused by variations like buffer manufacturing variation, power-ground noise, etc. contributes a large portion of the nominal skew. Robust clock network that is less sensitive to process variation is highly desirable. Non-tree clock network is a promising way to address the skew variation problem. Clock mesh, because of its inherent redundancy, is tolerant to process variation and is able to provide lower skew variability compared with traditional clock tree. However, clock mesh has the disadvantage of resulting in much more power dissipation. Link based non-tree clock network is an economic way to reduce clock skew caused by variations. However, it is still an open topic where links should be inserted in order to achieve largest skew reduction with smallest extra resources. In this project, we studied this variation-driven clock network construction problem, and research on both clock mesh construction and link-based clock tree construction.