3-D Floorplan Design

3-D chip is a viable solution to the interconnect problems caused by the increasing complexity of circuit design. In 3-D chips, there are several silicon layers, with metal layers in between for making connections. Traditional floorplanners consider only one layer of packing and a trivial extension to multiple layers will not work well because of the lack of information about inter-layer topological relationships. We have proposed a new floorplan representation, called Layered TCG, to perform 3-D floorplan design, which considers both intra-layer and inter-layer topological relationships between blocks. In the future, we will also consider the thermal problem (one of the biggest problems in 3-D chip design) and other interconnect issues in 3-D floorplan design.