3-D Floorplan Design
3-D chip is a viable solution to the interconnect problems caused by the increasing
complexity of circuit design. In 3-D chips, there are several silicon layers,
with metal layers in between for making connections. Traditional floorplanners consider
only one layer of packing and a trivial extension to multiple layers will not work
well because of the lack of information about inter-layer topological relationships.
We have proposed a new floorplan representation, called Layered TCG, to perform
3-D floorplan design, which considers both intra-layer and inter-layer topological
relationships between blocks. In the future, we will also consider the thermal problem
(one of the biggest problems in 3-D chip design) and other interconnect issues
in 3-D floorplan design.
3-D Floorplanning using Labeled Tree and Dual Sequences ,
Renshen Wang, Evangeline F.Y. Young, Yi Zhu, Fan Chung Graham, Ronald Graham and Chung-Kuan Cheng,
International Symposium on Physical Design, 2008.
Block Alignment in 3D Floorplan using Layered TCG ,
Jill H.Y. Law, Evangeline F.Y. Young and Royce L.S. Ching,
ACM Great Lakes Symposium on VLSI, pp.376-380, 2006.
- Law Hoi Ying, Jill (MPhil)
- RGC Earmarked Grant on "Interconnect-Driven Floorplanning for 3-D Chips" (2003-06)