Congratulations to Prof. Bei YU, along with other co-authors from UT Austin and Cadence for receiving Integration, the VLSI Journal Best Paper Award 2018. The Best Paper Award aims to recognize the best quality paper published in the journal over the past three years (i.e., from January 2015 to December 2017). The award is based on the overall quality, the originality, contributions, impacts, the subject matter and the timeliness of the research. In addition, the award includes a cash prize of $500 and a certificate plaque.

Title: Stitch aware Detailed Placement for Multiple E-Beam Lithography

Link: https://doi.org/10.1016/j.vlsi.2017.02.004

Abstract:

In multiple electron beam lithography (MEBL), a layout is split into stripes and the layout patterns are cut by stripe boundaries, then all the stripes are printed in parallel. If a via pattern or a vertical long wire is overlapping with a stitch, it may suffer from poor printing quality due to the so called stitch error; then the circuit performance may be degraded. In this paper, we propose a comprehensive study on the stitch aware detailed placement to simultaneously minimize the stitch error and optimize traditional objectives, e.g., wirelength and density. Experimental results show that our algorithms are very effective on modified ICCAD 2014 benchmarks that zero stitch error is guaranteed while the scaled half-perimeter wirelength is very comparable to a state-of-the-art detailed placer. In addition, our technique is very generic that it is applicable to many other placement targets, such as local congestion optimization, which is also demonstrated in the experimental results.