CENG2010 Digital Logic Design Laboratory

 

Course code CENG2010
Course title Digital Logic Design Laboratory
數字邏輯設計實驗
Course description This course aims at providing an intensive hands-on introduction to digital system design using a hardware description language (e.g. VHDL). Students will learn how to design, simulate and debug digital systems through lab exercises. Topics include the basic language syntax, signals/variables/constants declaration, data types, basic operators, concurrent and sequential statements, and structural modelings.
本科旨在密集介紹如何利用硬件描述語言(如 VHDL)設計數位邏輯系統。學生透過實驗學習數字系統的設計、模擬及調試技巧。主題包括基本設計語言語法、信號/變數/常數申明、數據類型、基本運算符、共時性/順序性敘述,及結構建模。
Unit(s) 1
Course level Undergraduate
Semester 1
Grading basis Graded
Grade Descriptors A/A-:  EXCELLENT – exceptionally good performance and far exceeding expectation in all or most of the course learning outcomes; demonstration of superior understanding of the subject matter, the ability to analyze problems and apply extensive knowledge, and skillful use of concepts and materials to derive proper solutions.
B+/B/B-:  GOOD – good performance in all course learning outcomes and exceeding expectation in some of them; demonstration of good understanding of the subject matter and the ability to use proper concepts and materials to solve most of the problems encountered.
C+/C/C-: FAIR – adequate performance and meeting expectation in all course learning outcomes; demonstration of adequate understanding of the subject matter and the ability to solve simple problems.
D+/D: MARGINAL – performance barely meets the expectation in the essential course learning outcomes; demonstration of partial understanding of the subject matter and the ability to solve simple problems.
F: FAILURE – performance does not meet the expectation in the essential course learning outcomes; demonstration of serious deficiencies and the need to retake the course.
Learning objectives At the end of the course of studies, students will have acquired
1. the concepts in using hardware description language(s) (HDL) for digital system design;
2. the techniques in using design automation tools for design entry, synthesis, simulation and implementation;
3. the experiences in testing and debugging digital systems on development boards 
Learning outcomes At the end of the course of studies, students will have acquired the ability to
1. apply concepts and methods of digital system design techniques;
2. design combinational and sequential digital systems using hardware description language (HDL);
3. analyze the results of logic and timing simulations and debug digital systems.
Assessment
(for reference only)
Assignments: 50%
Exam: 50%
Recommended Reading List 1. Digital Design with RTL Design, VHDL, and Verilog, 2/e, by Frank Vahid;
2. VHDL for Digital Design, by Frank Vahid & Roman Lysecky

 

CENGN programme learning outcomes Course mapping
Upon completion of their studies, students will be able to:  
1. identify, formulate, and solve computer engineering problems (K/S); P
2. design, implement, test, and evaluate a computer system, component, or algorithm to meet desired needs (K/S);
P
3. receive the broad education necessary to understand the impact of computer engineering solutions in a global and societal context (K/V);
4. communicate effectively (S/V);
5. succeed in research or industry related to computer engineering (K/S/V);
P
6. have solid knowledge in computer engineering, including programming techniques, circuit design, micro-system prototyping, solid state device development, algorithms and theory, etc. (K/S); P
7. integrate well into and contribute to the local society and the global community related to computer engineering (K/S/V);
8. practise high standard of professional ethics (V);
9. draw on and integrate knowledge from many related areas (K/S/V);
Remarks: K = Knowledge outcomes; S = Skills outcomes; V = Values and attitude outcomes; T = Teach; P = Practice; M = Measured