UGC Direct Grant (96-97, as Principal Investigator).

RGC Earmarked Grant (97-99, as Principal Investigator) "A New FPGA Ar chitecture and Design Automation Methodology for High Chip Performance and Fast Circuit Mapping".

UGC Direct Grant (98-99, as Principal Investigator).

RGC Earmarked Grant (99-01, as Principal Investigator) "A Performance -Driven Synthesis System Targeted for Deep Sub-Micron Technology".

UGC Direct Grant (00-02, as Principal Investigator).

RGC Earmarked Grant (01-03, as Principal Investigator) "A Graph-based Rewiring Scheme for Boolean Networks and its Applications for New FPGA Design Automations".

Dean's INL Grant (01-02, as PI).

NSFC/RGC HK/China Joint Research Grant (02-05, as PI, joint project with Tsi nghua CAD group).

RGC Earmarked Grant (03-05, as Principal Investigator) "Applying Optimal Switch Box Designs for FPGA Architecture and Communication Switching Network".

UGC Direct Grant (04-05, as Principal Investigator).

UGC Direct Grant (05-06, as Principal Investigator).

RGC Earmarked Grant (06-08, as Principal Investigator) "Theory Refinements and New FPGA Synthesis Applications for Logic Rewiring Techniques".

NSFC (No. 90607001, 1/7/2006-31/12/2008, Co-Investigator) " The Architecture and Key Technologies of Programmable and Configurable SOC".

ITSP (ITS/113/07, 1/9/2007-31/8/2008, Pricipal Investigator) " Interconnection-Based New Circuit Optimization Technique for Electronic Design Automation".

UGC Direct Grant (08-10, as Principal Investigator).

Seed Fund CUHK (09-10, as Principal Investigator).

RGC Earmarked Grant (09-11, as Principal Investigator) "Rewiring-based Combinational and Sequential Structural Synthesis on Clocking Network for Low Power and High Performance".

ITF Tier2 (ITS/261/09FP, 1/1/2010-31/12/2011, Pricipal Investigator) " New Interconnect-centered VLSI/CAD Techniques for High-Performance ASIC Designs".