Book Chapters/Lecture Notes

  • W.Q. Huang, Y.L. Wu, and C. K. Wong, "A Cogitative Algorithm for Solving the Equal Circles Packing Problem," Handbook of Combinatorial Optimization, Vol. A, pp. 591-605, Kluwer Academic Publishers Edited by DingZhu Du and Panos Pardalos, 1999.

  • Y.L. Wu, J. Sum, F.C. Lau, C.S. Yeung, and C. Lau, "Design Issues of a Mobile Trading System Using Hand-held PC," World Wide Web: Technologies and Applications for the New Millennium, Chapter 12, Computer Science Research, Education, and Applications Press, Jan. 2000.

  • Chun Gu, and Y.L. Wu, "An Improved Pattern Processing Based Heuristic of OBDD Variable Ordering", Lecture Notes in Operations Research. pp. 84-95, World Publishing Corporation, Aug. 1998.

    Conferences

  • S.C. Fu, T.K. Lam, and Y.L. Wu, "On Improved Scheme for Digital Circuit Rewiring and Application on Further Improving FPGA Technology Mapping," Proc. ASP-DAC 2009.

  • T.K. Lam, W.C. Tang, W.H. Lo, and Y.L. Wu, "FPGA Technology Mapping Optimization by Rewiring Algorithms Cooperating with Lossless Synthesis," Proc. IPS 2008.

  • M.Q. Jiang, W.C. Tang, F.Y. Young, and Y.L. Wu, "Beyond Optimal Retiming" Rewiring for Effective Flip-flop Reduction," Proc. IPS 2008.

  • H.B. Fan, and Y.L. Wu, "Customized Reconfigurable Interconnection Networks for Multiple Application SoCs ," Proc. FPL'08. pp. . Germany 2008

  • X. Xiong, Y. L. Wu and W. B. Jone, "Material Fatigue and Reliability of MEMS Accelerometers," to appear in Proc. DFT'08 2008.

  • H.B. Fan, C. Hundt, Y.L. Wu, and J. Ernst, "Algorithms and Implementation for Interconnection Graph Problem," to appear Proc. International Conference on Combinatorical Optimization and Applications (COCOA'08). pp. . Canada 2008

  • W.C. Tang, and Y. L. Wu, et al. "A Quantitative Study of the Routing Architecture Exploiting Routing Locality Property for Better Performance and Routability," to appear Proc. The International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA'08) pp. . Las Vegas USA. 2008.

  • H.B. Fan, and Y.L. Wu, "Interconnection Graph Problem," Proc. International Conference on Foundations of Computer Sciecne (FCS'08). pp. . Canada 2008

  • F.S. Chim, and Y.L. Wu, "On Extended Graph-Based Rewiring Technique," Proc. IEEE ASICON 2007. pp. 114-107.

  • W.C. Tang, W.H. Lo, and Y.L. Wu, "How Many Flip-foops Can we save by Coupling Retiming and Rewiring?" Proc. IPS 2007. pp. 97-100. (Best Presentation Award)

  • W.H. Lo, W.C. Tang, and Y.L. Wu, "Further Improving Optimal Retiming with Logic Perturbation," Proc. IPS 2007. pp. 100-103.

  • L. Zhou, W.C. Tang, and Y. L. Wu, "Fast Placement-Intact Logic Perturbation Targeting for FPGA Performance Improvement," Proc. IEEE Southern Conference on Programmable Logic (SPL'07) pp. 63-68, 2007. Argentina. (Celoxica Best Paper Award)

  • L. Zhou, W.C. Tang, W.H. Lo, and Y.L. Wu, "How Much Can Logic Perturbation Help from Netlist to Final Routing for FPGAs," (to appear) Proc. IEEE/ACM Design Automation Conference (DAC'07), 2007.

  • W.C. Tang, W.H. Lo, and Y.L. Wu, "Further Improve Excellent Graph-Based FPGA Technology Mapping by Rewiring," (to appear) Proc. ISCAS 2007. New Orlean.

  • L. Zhou, Y. L. Wu, and W.C. Tang, "Use Augmented Connection Boxes to Improve FPGA Performance," Proc. ICCCAS pp. 2469-2473, 2006.

  • X. Xiong, Y. L. Wu and W. B. Jone, "Reliability Analysis of Self-Repairable MEMS Accelerometer," to appear in Proc. Defect and Fault Tolerance in VLSI Systems 2006.

  • Wing-Hang Lo, and Y. L. Wu, "Improving Single-Pass Redundancy Addition and Removal with Inconsistent Assignments," Proc. VLSI-DAT pp. 175-178, April. 2006.

  • S. Wei, S. Dong, X. Hong, and Y. L. Wu, "On Handling the Fixed-outline Constraints Using Less Flexibility First Principles," to appear in Proc. IEEE ISCAS, Greece, May, 2006.

  • X. Xiong, Y. L. Wu and W. B. Jone, "Design and analysis for self-repairable MEMS Accelerometer," Proc. Defect and Fault Tolerance in VLSI Systems pp. 21-29, Oct. 2005. Monterey, California.

  • X. Xiong, Y. L. Wu and W. B. Jone, "Yield analysis for self-repairable MEMS devices," Proc. Midwest Symposium on Circuits and Systems (MWSCAS) pp. 359-362, 2005.

  • S. Wei, S. Dong, X. Hong, and Y.L. Wu, "A Comaprison of Less Flexibility First Principles with Simulated Annealing," Proc. IEEE Midwest Symposium on Circuits and Systems (MWSCAS) 2005.

  • Z. Zhou, S. Dong, X. Hong, Y.L. Wu, and Kajitani Yoji, "A New Approach based on LFF for Optimization of Dynamic Hardware Recognitions," Proc. IEEE ISCAS 2005.

  • H.B. Fan and Y.L. Wu, "On Three-Stage Interconnection Networks for Group Communications," (invited talk) Proc. IEEE Emerging Information Technology Conference (EITC) 2005. Taipei.

  • S. Wei, S. Dong, X. Hong, and Y.L. Wu, "A Fast Placement Approach for Large Scale Modules Based on Less Flexibility First Principles," Proc. IEEE ASICON05 pp. 780-783, 2005.

  • J. Yuan, S. Dong, X. Hong, and Y.L. Wu, "VLSI Floorplan Based on Less Flexibility First Principle and Linear Programming," Proc. IEEE ASICON05 pp. 832-835, 2005.

  • T. Liu, W.M. Wu, Y.L. Wu, and J.N. Bian, "Hexagon/Triangle Packing Using Improved Least Flexibility First Principle Algorithm," Proc. IEEE ASICON05 pp. 828-831, 2005.

  • Y.L. Wu, and C.K. Chan, "On Improved Least Flexibility First Heuristics Superior for Packing and Stock Cutting Problems," Proc. 3rd Symposium on Stochastic Algorithms, Foundations and Applications, pp. 70-81, 2005. Moscow.

  • Rongjun Mu, Jinian Bian, Yu-Liang Wu, and Wai-Chung Tang, "Further Minimization of Binary Decision Diagrams of Large Circuits," Proc. CAID&CD 2005 Conference Delft, Netherlands, pp. 551-555, 2005.

  • Yuen-Ting Wu and Y.L. Wu, "A Less Flexibility First Based Algorithm for Container Loading Problems," Proc. Operations Research International Conference. pp. 368-375, 2005.

  • H. Fan, Y.L. Wu, and L. Zhou, "Augmented Disjoint Switch Boxes for FPGAs," Proc. WISICT, 2005. pp. 129-134. 2005.

  • H. Fan, and Y.L. Wu, "Crossbar Based Design Schemes for Optimal Switch Boxes and Programmable Interconnection Networks," Proc. ASP-DAC, 2005. pp. 910-915. 2005.

  • J. Yuan, S.Q. Dong, X.L. Hong, and Y.L. Wu, "LFF Algorithm for Heterogeneous FPGA Floorplanning," Proc. ASP-DAC, 2005. pp. 1123-1126. 2005.

  • Wai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu, and Shih-Chieh Chang, "FPGA Technology Mapping Optimization by Rewiring Algorithms," Proc. ISCAS, 2005. pp. 5653-5656, 2005.

  • H. Fan, Y.L. Wu, J. Liu, and C.C. Cheung, "On Optimal Irregular Switch Box Designs," Proc. FPL'04. pp. 189-199. Belgium.

  • L. Zhou, C.C. Cheung. and Y.L. Wu, "What if Merging Connection and Switch Boxes - an Experimental Revisit on FPGA Architectures," Proc. IEEE ICCCAS, 2004. pp. 1295-1299. (Best Paper Award)

  • Chi-Kit Ho, and Y.L. Wu, "Logic Synthesis System with Standard GBAW Patterns as Building Units," Proc. IEEE ICCCAS, 2004. pp. 1238-1242.

  • L. Zhou, and Y.L. Wu, "Optimal MST-Based Graph Algorithm on FPGA Segmentation Design," Proc. IEEE ICCCAS, 2004. pp. 1290-1294.

  • Z. Yang, S. Dong, X. Hong, and Y.L. Wu, "Interconnection Driven VLSI Module Placement Based on Quadratic Programming and Considering Congestion Using LFF Principles," Proc. IEEE ICCCAS, 2004. pp. 1243-1247.

  • Dong Xiang, Ming-Jing Chen, and Yu-liang Wu, "Scan-Based BIST Using an Improved Scan Forest Architecture," Proc. ATS'04. pp. 88-93, 2004

  • Y.L. Wu, C.K. Chan, SQ Dong, and XL Hong, "Effective Least Flexibility First Heuristics for Rectangle Packing and Stock Cutting," Abstract collection. CORS/INFORMS, 2004. pg. 21. Banff.

  • S. Dong, Z. Yang, X Hong, and Y.L. Wu, "Module Placement Based on Quadratic Programming and Rectangle Packing Using LFF Principle," Proc. ISCAS, pg. V61-V64, 2004.

  • Xingguo Xiong, Y.L. Wu, and Wen-Ben Jone, "A Dual-Mode Built-in Self-test Technique for Capacitive MEMS Devices," Proc. IEEE VLSI Test Symposium. pp. 148-153, 2004

  • Dong Xiang, Shan Gu, and Y.L. Wu, "A Cost-Effective Scan Architecture for Scan Testing with Non-Scan Test Power and Test Application Cost," Proc. IEEE/ACM DAC'03. pp. 744-747, 2003 Anaheim.

  • Z. Yang, S. Dong, X Hong, and Y.L. Wu, "LFF-based Interconnect-driven VLSI Placement Algorithm," Proc. CNCC-03 (in Chinese).

  • W. Tang, W. Lo, T. Lam, K. Mok, C. Ho, H. Yeung, H. Fan, and Y.L. Wu, "A Quantitative Comparison and Analysis on Rewiring Techniques," Proc. IEEE ASICON'03. pp. 242-245, Oct. 2003.

  • Z. Yang, S. Dong, X. Hong, and Y.L. Wu, "VLSI Placement with Arbitrary Rectilinear Block with Less Flexibility First Principles," Proc. IEEE ASICON'03. pp. 225-228, Oct. 2003.

  • J. Bian, H. Xue, Z. Xu, L. Xu, Y. Wang, and Y.L. Wu, "Local Logic Substitution algorithm for Post-Layout Re-synthesis," Proc. IEEE ASICON'03. pp. 136-139, Oct. 2003.

  • Y.L. Wu, H. Fan, and C.C. Cheung, "On Strong Locality Properties of Alternative Wires in Digital Circuits," Proc. SASIMI'03. pp. 244-250, 2003 Hirosima.

  • J. Liu, H. Fan, and Y.L. Wu, "On Improving FPGA Routability Applying Multi-level Switch Boxes," Proc. IEEE ASP-DAC'03. pp. 366-369, 2003 Kitakyushy.

  • H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, "On Optimum Designs of Universal Switch Blocks," Proc. IEEE International Conference on Field Programmable Logic and Applications (FPL). pp. 142-151, 2002 Montpellier.

  • H. Fan, J. Liu, D. D. Porto, and Y.L. Wu, "A Detailed Routing Algorithm for Switch Box of Optimum Routability," Proc. IEEE International Conference on Circuits/Systems Computers and Communications (ITC-CSCC). pp. 1732-1735. 2002 Phuket.

  • S. Dong, X. Hong, Y.L. Wu, Z. Xiu, J. Gu, "VLSI Placement with Pre-placed Modules Based on Less Flexibility First Principles," in Proc. IEEE International Conference on ASIC (ASICON). pp. 106-109, Oct. 2001. Shanghai.

  • S. Dong, X. Hong, and Y.L. Wu, et.al. "Module Placement on Arbitrary Rectilinear Regions using Less Flexibility First Principles," Proc. CAD/CG 2001.

  • H. Fan, J. Liu, Y.L. Wu, and Chak-Chung Cheung, "On Optimum Switch Box Designs for 2-D FPGAs," Proc. IEEE/ACM Design Automation Conference (DAC). pp. 203-208, June. 2001. Las Vegas.

  • Chak Chung Cheung, Y.L. Wu, and D. Ihsin Cheng, "Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques," in Proc. IEEE DATE. pp. 233-239, March. 2001. Munich.

  • Chin Ngai Sze, and Y.L. Wu, "Improved Alternative Wiring Scheme Applying Dominator Relationship," in Proc. IEEE ASPDAC'01. pp. 473-478, Jan. 2001. Yokohama.

  • H. Fan, J. Liu, and Y.L. Wu, "Combinational Routing Analysis and Design of Universal Switch Blocks," in Proc. IEEE ASPDAC'01. pp. 641-648, Jan. 2001. Yokohama.

  • S. Dong, Y. Lin, X. Hong, Y.L. Wu, J. Gu, "VLSI Block Placement Using Less Flexibility First Principles," in Proc. IEEE ASPDAC'01. pp. 601-604, Jan. 2001. Yokohama.

  • H.B. Fan, J.P. Liu, and Y.L. Wu, "General Models for Optimum Arbitrary-Dimension FPGA Switch Box Designs," Proc. IEEE International Conference on Computer-Aided Design (ICCAD). pp. 93-98, Nov. 2000, San Jose.

  • Y.L. Wu, C.N. Sze, C.C. Cheung, and H.B. Fan, "On Improved Graph-Based Alternative Wiring Scheme for Multi-level Logic Optimization," Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS'00). pp. 654-657, Dec. 2000, Lebanon.

  • H.B. Fan, J. Liu, and Y.L. Wu, "A Global Routing Model for Universal Switch Box Design," Proc. IEEE International Conference on Electronics, Circuits and Systems (ICECS'00). pp. 78-81, Dec. 2000, Lebanon.

  • Y.L. Wu, and X.L. Yuan, "An Effective Approach for Circuit Cut-width Estimation," Proc. CAD&CG Sep. 2000. (also appear in journal of Computer Applications)

  • H.B. Fan, J.P. Liu, and Y.L. Wu, "A New FPGA Global Routing Model - A Decomposition Theory and Its Application", Proc. The 11th VLSI Design/CAD Symposium, pp. 103-106, Aug. 2000.

  • Y.L. Wu, W.N. Long, and H.B. Fan, "A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks," Proc. IEEE/ACM International VLSI Design 2000, pp. 268-273, Calcutta. (Honorable Mention Award) Jan. 2000.

  • W.N. Long, Y.L. Wu, and J.N. Bian, "IBAW: An Implication-Tree Based Alternative-Wiring Logic Transformation Algorithm," Proc. IEEE ASPDAC'00, pp. 415-421, Yokohama, Jan. 2000.

  • Y.L. Wu, X.L. Yuan, and I. Cheng, "Circuit Partitioning with Coupled Logic Restructuring Techniques," Proc. IEEE ASPDAC'00, pp. 655-660, Yokohama, Jan. 2000.

  • Jing Ding, and Y.L. Wu, "On Bit Transition Count and its Aliasing Estimation for Sequential Logic Circuits," Proc. IEEE ISPACS'99, pp. 477-480, Dec. 1999, Phuket, Thailand.

  • W.N. Long, Y.L. Wu, and J.N. Bian, "On Implication-Tree Based Redundancy Addition and Removal Algorithm," Proc. IEEE ISPACS'99, pp. 53-56, Dec. 1999, Phuket, Thailand.

  • J.L. Wu, and Y.L. Wu, "The Vertex Linear Aboricity of Claw-Free Graphs," Proc. NCCAS'99, pp. 206- 209, NOV. 1999.

  • Jing Ding, and Y.L. Wu, "Test Response Compaction for Sequential Logic Circuits," Proc. International Conf. on CAD/CG'99, pp. 726-730, Dec. 1999, Shanghai.

  • X.L. Yuan, Y.L. Wu, and D.Y. Gao, "Circuit Partitioning Using Graph-Based Alternative Wiring Technique," Proc. International Conf. on CAD/CG'99, pp. 647-651, Dec. 1999, Shanghai.

  • Y.L. Wu, and H.B. Fan, "On Local Configuration Analysis of Alternative Wires in Boolean Networks," Proc. IEEE ITC-CSCC'99, pp. 868-871, July. 1999. Niigata, Japan.

  • Y.L. Wu, J. Sum, F.C. Lau, C.S. Yeung, and C. Lau, "Design Issues of a Mobile Trading system Using Hand-held PC," Proc. APWEB'99, pp. 93-99, Sep. 1999. Hong Kong.

  • Jing Ding, and Y.L. Wu, "On the Testing Quality of Random and Pseudo-Random Sequences for Permanent and Intermittent Faults," Proc. IEEE ASP-DAC'99, pp. 311-314, Jan. 1999.

  • J. F. Pan, Y.L. Wu, and C. K. Wong, "On the Optimal Sub-Routing Structures of 2-D FPGA Greedy Routing Architectures," Proc. IEEE ASP-DAC'98. pp. 535-540, Feb. 1998. Yokohama.

  • Y.L. Wu, H.B. Fan, and C. K. Wong, "On Thin Boolean Functions and Related Optimal OBDD Ordering," Proc. IEEE International Conference on Computer Design (ICCD). pp. 216-218, Oct. 1998. Austin.

  • Jing Ding, Y.L. Wu, "New Test Response Compaction Approaches for Testing of Logic Circuits", Proc. International Conference on ASIC. pp. 427-430, Oct. 1998. Beijing.

  • Chun Gu, and Y.L. Wu, "An Improved Pattern Processing Based Heuristic of OBDD Variable Ordering", Proc. International Symposium on Operations Research and its Applications (same as BC3) pp. 84-95, Aug. 1998. Kumming.

  • Chun Gu, Y.L. Wu, L.K. Mak, and P.K. Cheuk, "Performance-Driven Post-Placement Synthesis for 2-D Regular Segmented FPGAs", Proc. International Conference on ASIC. pp. 314-317, Oct. 1998. Beijing.

  • H. Fan, Y.L. Wu, and C. K. Wong, "On Fixed Edges and Edge-Reconstruction of Series-Parallel Networks," Proc. IEEE APCCAS: Microelectronic and Integration System. pp. 707-710, Nov. 1998. Thailand.

  • Y.O. Tam, Y.L. Wu, W. Huang, and C. K. Wong, "An Effective Quasi-Human Based Heuristic for Solving Rectangle Packing Problem," Proc. IEEE APCCAS: Microelectronic and Integration System. pp. 137-140, Nov. 1998. Thailand.

  • J.C. Rau, W.B. Jone, S.C. Chang, and Y.L. Wu, "A Tree-Structured LFSR Synthesis Scheme for Pseudo-Exhaustive Testing of VLSI Circuits," Proc. IEEE International Testing Conference (ITC). pp. 322-330, Oct. 1998. Washington, D. C.

  • Y.L. Wu, Douglas Chang, Malgorzata Marek-Sadowska, and Shuji Tsukiyama, "Not Necessarily More Switches More Routability", Proc. IEEE ASP-DAC, pp. 579-584 1997. (nominated Best Paper Award)

  • C.C. Lin, D. Chang, Y.L. Wu, and M. Marek-Sadowska, "Time-Multiplexing Routing Resource for FPGA Architecture," Proc. IEEE Custom Integrated Circuits Conference (CICC)., pp. 152-155, 1996.

  • Y.L. Wu, and Douglas Chang, "On Switch Box Topology Implications upon FPGA Routability", Proc. 7th VLSI Design/CAD Symposium, pp. 203-206, 1996.

  • Y.L. Wu and M. Marek-Sadowska, "Routing for Regular Segmented 2-D FPGAs," Proc. IEEE ASP-DAC, pp. 329-334, 1995.

  • Y.L. Wu and M. Marek-Sadowska, "Orthogonal Greedy Coupling - A New Optimization Approach to 2-D FPGA Routing," Proc. IEEE Design Automation Conference (DAC), pp. 568-573, 1995.

  • Y.L. Wu and M. Marek-Sadowska, "An Efficient Router for 2-D FPGAs," Proc. IEEE European Design Automation Conference, pp. 412-416, 1994.

  • Y.L. Wu, and D. Chang, "On the NP-completeness of Regular 2-D FPGA Routing Architectures and a Novel Solution," Proc. IEEE International Conference on Computer-Aided Design (ICCAD), pp. 362-366, 1994.

  • Y.L. Wu, S. Tsukiyama, and M. Marek-Sadowska, "On Computational Complexity of a Detailed Routing Problem in Two-Dimensional FPGAs," Proc. 4th Great Lakes Symp. on VLSI, pp. 70-75, 1994.

  • Y.L. Wu, S. Tsukiyama, and M. Marek-Sadowska, "Computation Complexity of 2-D FPGA Routing for Arbitrary Switch Box Topologies," Proc. of FPGA Workshop, 1994., pp. 70-75, 1994.

  • Y.L. Wu and M. Marek-Sadowska, "Graph Based Analysis of FPGA Routing," Proc. IEEE EURO-DAC with EURO-VHDL, pp. 104-109, 1993.

  • Y.L. Wu and M. Marek-Sadowska, "Efficient Ordered Binary Decision Diagrams Minimization Based on Heuristics of Cover Pattern Processing," Proc. IEEE European Design Automation Conference, 1993.