WU, David Yu - Liang Professor Ph.D. (UCSB), MIEEE, MIEICE

Dr. Yu-Liang (David) Wu received his MS degree in Computer Science from Univ of Miami in 1984 and the Ph.D. degree in Electrical and Computer Engineering from University of California at Santa Barbara in 1994. On 1985, he worked in Internet Systems Corporation as a system programmer on network communication protocols (DARPA TCP/IP, Telnet). From 1986 to 1988, he worked at AT&T Bell Labs on the development of several telephone operation systems. From 1988 to 1989, he worked for Amdahl Corporation on tester software designs for super computers. Before he joined the Chinese University of Hong Kong in January 1996, he had worked at Cadence Design Systems Incorporation as a senior MTS since December 1994, where he worked in the R&D of the silicon synthesis product (PBS) targeting at bridging the gap between logic and physical level optimizations for deep-submicron chip designs. His current research interests mainly relate to EDA (VLSI CAD) optimization of logical and physical designs for VLSI circuits, optimal FPGA, switching structure/system designs, and some multi-core issues.

Address: Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, N.T. Hong Kong

Research Interests/Grants

• Silicon synthesis for Deep-Submicron technology, particularly on pre-analyzed pattern based Circuit Rewiring and Logic Synthesis techniques and systems.
• SoC IP Core designs for op timal group communication networks, new FPGA siwtching boxes, architectures (Our home-brew (manual design) FPGA chip design example), SoC On-Chip-Networks and related CAD tools.
• Algorithm, combinatorial optimization for VLSI designs/testing, particularly on optimization techniques invloving multiple objectives.
• Architecture-driven logic/physical design automations.
• 2D/3D Cutting and Packing

VLSI EDA/Testing PGS Seminar

Teaching Assignment

• CENG3490 VLSI Design (Emphasis: Manual system (whole chip) design, Advanced logic design techniques, Introductory logic synthesis, testing)

• CENG5271 EDA (VLSI CAD) for Logic Design of Digital Systems

Professional Services

A few works (with students and collaborating partners)

Publications: (selected journals)

• T.K. Lam, W.C. Tang, X.Q. Yang, Y.L. Wu, "ECR: A Powerful and Low Complexity Error Cancellation Rewiring Scheme," to appear ACM Transactions on Design Automation of Electronic Systems (TODAES) 2012.

• H. Fan, Brian Moore, and Y.L. Wu, "Structured Overlay Network for File Distribution," to appear Discrete Mathematics, Algorithms and Applications. Vol. 4, No. 2(2012) pp. 12500-1 - 12500-15, June, 2012.

• F. S. Chim, T. K. Lam, Y.L. Wu, and F, H. Fan, "On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, to appear, Vol. E94, No. 12, pp. Dec. 2011.

• D. Ramakrishnan, Y. L. Wu and W. B. Jone, "Design and Analysis of Location Cache in a NoC-Based Chip Multiprocessor System," ASP Journal of Low Power Electronics (JOLPE) Vol. 6, No. 2, pp.240-262, Aug. 2010.

• X. Xiong, Y. L. Wu and W. B. Jone, "Yield analysis for self-repairable MEMS devices," Analog Integrated Circuits and Signal Processing 56:1/2 pp.1-11, Auguest. 2008.

• H. Fan, J. Liu, Y.L. Wu, and C.C. Cheung, "The Exact Channel Density Bound and Compound Design for Generic Universal Switch Blocks," ACM Transactions on Design Automation of Electronic Systems (TODAES). Vol. 12, No. 2, April, 2007.

• H. Fan, Y.L. Wu, Chak-Chung Cheung, and J. Liu, "Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes and Rearrangeable Switch Box Designs," IEEE Transactions on Computers. Vol. 55, No. 4, pp. 373-384, April, 2006.

• Xingguo Xiong, Y.L. Wu, and Wen-Ben Jone, "A Dual-Mode Built-in Self-Test Technique for Capacitive MEMS Devices," IEEE Transactions on Instrumentation and Measurement, Vol. 54, No. 5, pp. 1739-1750, Oct. 2005

• H. Fan, J. Liu, Y.L. Wu, and Chak-Chung Cheung, "On Optimal Hyper-universal and Rearrangeable Switch Box Designs," IEEE Transactions on Computer-Aided Design. Vol. 22, No. 12, pp. 1637-1649, Dec. 2003.

• Y.L. Wu, C.C. Cheung, D.I. Cheng, and H.B. Fan, "Further Improve Circuit Partitioning using GBAW Logic Perturbation Techniques," IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Vol. 11, No. 3, pp. 451-460, June. 2003.

• H.B. Fan, J.P. Liu, and Y.L. Wu, "General Models and a Reduction Design Technique for FPGA Switch Box Designs," IEEE Transactions on Computers. Vol. 52, No. 1, pp. 21-30. Jan. 2003.

• J. Liu, H. Fan, D. Porto, and Y.L. Wu, "An Efficient Exact Router for Hyper-Universal Switching Box," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E86-A No. 6, pp. 1430-1436, June 2003.

• C.N. Sze, W.N. Long, Y.L. Wu, and J.N. Bian, "Accelerating Logic Rewiring Using Implication Analysis Tree," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol. E85-A, No. 12, pp. 2725~2736, Dec. 2002.

• H. Fan, J. Liu, Y.L. Wu, and C.K. Wong, "Reduction Design for Generic Universal Switch Blocks," ACM Transactions on Design Automation of Electronic Systems (TODAES). Vol. 7, No. 4, pp.526-546, 2002

• Y.L. Wu, W.Q. Huang, S.C. Lau, C.K. Wong, and G.H. Young, "En Effective Quasi-Human Based Heuristic for Solving the Rectangle Packing Problem," European Journal of Operational Research (EJOR), issue 141/2, pp. 341-359, Sep. 2002.

• H.B. Fan, Y.L. Wu, and Y.W. Chang, "Comment on General Universal Switch Blocks," IEEE Transactions on Computers. Vol 51. No. 1, pp. 93-95, Jan. 2002.

• Y.L. Wu, H.B. Fan, M. Marek-Sadowska, and C.K. Wong, "OBDD Minimization Based on Two-Level Representation of Boolean Functions," IEEE Transactions on Computers. Vol. 49, No. 12, pp. 1371-1379, Dec. 2000.

• Y.L. Wu, W.N. Long, and H.B. Fan, "A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol. E83-A, No.6, June 2000

• Y.L. Wu, D. Chang, M. Marek-Sadowska, and S. Tsukiyama, "On Improved FPGA Greedy Routing Architecture," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. Vol. E81-A, No. 12, pp. 2485~2491, Dec. 1998.

• Y.L. Wu, and M. Marek-Sadowska, "On Regular Segmented 2D FPGA Routing," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, Vol. E80-A, No. 10, pp. 1871- 1877, Oct. 1997.

• Y.L. Wu and M. Marek-Sadowska, "Routing for Array Type FPGAs," IEEE Transactions on Computer Aided Design. pp. 506-518, May 1997.

• Y.L. Wu, S. Tsukiyama, and M. Marek-Sadowska, "Graph Based Analysis of 2-D FPGA Routing," IEEE Transactions on Computer-Aided Design, pp. 33-44, Jan. 1996.

  Book Chapters/Conferences

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