| Title: | Hardware/Software Partitioning and Scheduling with Partial Runtime-Reconfigurable FPGAs |
| Date: |
March 28, 2008 (Friday)
|
| Time: |
4:30 p.m. - 5:30 p.m.
|
| Venue: |
Room 1021, 10/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong, Shatin, N.T. |
| Speaker: |
Dr. Zonghua Gu
Assistant Professor Department of Computer Science and Engineering Hong Kong University of Science and Technology |
Reconfigurable HW devices, such as FPGAs, are very popular in today's embedded systems design due to their low-cost, high-performance and reconfigurability. FPGAs are inherently parallel, that is, two or more tasks can execute on a FPGA device concurrently as long as they can both fit on it. Partially Runtime-Reconfigurable (PRTR) FPGAs, such as Virtex-2 Pro and Virtex-4 from Xilinx, allow part of the FPGA area to be reconfigured while the remainder continues to operate without interruption, so that HW tasks can be placed and removed dynamically at runtime. I discuss the problem of optimal hardware/software partitioning and static task scheduling for a hybrid FPGA/CPU device, with possible optimization objectives of minimizing latency, minimizing power consumption or maximizing throughput.
BIOGRAPHY:
Dr. Zonghua Gu is an assistant professor in the Department of Computer Science and Engineering at HKUST. He joined HKUST in 2005. He holds a Ph.D. degree from the University of Michigan at Ann Arbor. http://www.cse.ust.hk/~zgu/
Enquiries: Miss Temmy So at tel 2609 8444
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar