The Chinese University of Hong Kong
Department of Computer Science and Engineering

Seminar

Title: Bit-level versus packet-level analysis of communication systems
Date: July 3, 2007 (Tuesday)
Time: 4:00 p.m. - 5:00 p.m.
Venue: Room 1027, 10/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
Shatin, N.T.
Speaker: Dr. Gerardo Rubino
Senior Researcher
INRIA
France

ABSTRACT:

This talk describes a new paradigm we are proposing to analyze the performance of nodes in a communication network. Assume the following textbook case: variable-size packets arrive at an output link of a node according to a Poisson process (of course, unrealistic) with rate r in pps (packets per sec). The buffer associated with the link is large enough, so we neglect losses. The link speed is equal to c bps (bits per sec). The packets have a very variable length in bits, and we decide to represent it by an exponential random variable with mean B in bits. The question is: how much memory is occupied in the buffer, on the average, if the system is stable and in equilibrium? The standard answer is: at the packet level, this is an M/M/1 model with arrival rate r pps and service rate c/B pps. The system is stable iff r < c/B and, in that case, the average occupied memory is B rho /(1 - rho) bits, where rho = r/(c/B) < 1 is the load of the system.

We claim that this answer misrepresents the dynamics of the system, without any change in the assumptions above. This happens because of the implicit assumptions about the way memory is used hidden in the standard answer, and, in particular, the way memory is freed. We provide an alternative analysis taking into account the usual way memory is managed in a communication node. The analysis is done in the more general M/G/1 case, leading to a new Pollaczec-Khintchine-like formula, and we provide more results in other situations, all illustrating the same phenomenon. Some supplementary simulation results on more complex cases where buffers are limited in size, thus leading to packet losses, provide arguments supporting the interest of the new proposed bit-level view.

BIOGRAPHY:

G. Rubino is a senior researcher at INRIA. It is the head of the Dionysos team at the Rennes Unit of INRIA, a research group specialized in networking analysis (through stochastic modeling) and design. His main research areas are in applied probability models, and in quality evaluation (QoS, QoE). He has held professor positions at the ENST Bretagne engineering school, Brittany, France, and at the university of the Republic, Montevideo, Uruguay. He presently belongs to the IFIP WG 7.3 (Computer System Modeling and Performance Evaluation).

Enquiries: Miss Temmy So at tel 2609 8444

For more information, please refer to http://www.cse.cuhk.edu.hk/seminar

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