Title:	Coping with defects and process variations - a new opportunity for FPGAs
Date:	February 5, 2007 (Monday)
Time:	2:30 p.m. - 3:30 p.m.
Venue:	Room 121, 1/F, Ho Sin-hang Engineering Building, The Chinese University of Hong Kong, Shatin, N.T.
Speaker:	Professor Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College United Kingdom

ABSTRACT:

Technology improvement in the future is expected to result in significant increase in defects and large variations in many process parameters. The consequence of this trend is to reduce the manufacturing and parametric yield for integrated circuits. In this talk, a number of issues relating to potential yield improvement in FPGAs will be addressed. The reconfigurable nature of FPGAs are exploited to cope with both catastrophic defects and parametric yields through redundancy and run-time configurations. The potential gains of these approaches for 65nm technology and beyond are explored.

BIOGRAPHY:

Peter Y. K. Cheung is a professor of digital systems and deputy head of the Department of Electrical & Electronic Engineering at Imperial College. His research in VLSI architectures and reconfigurable systems has led to a number of successful industrial products with LSI Logic and Sony, and has resulted in over 120 papers in peer-reviewed journals and conference proceedings, 4 books and 3 patents.

Enquiries: Miss Temmy So at tel 2609 8444

For more information, please refer to http://www.cse.cuhk.edu.hk/seminar