| Title: | Testing System Chips |
| Date: |
January 15, 2007 (Monday)
|
| Time: |
2:30 p.m. - 3:30 p.m.
|
| Venue: |
Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong, Shatin, N.T. |
| Speaker: |
Professor Erik Larsson
Associate Professor (Docent) Department of Computer and Information Science Linkopings Universitet Sweden |
Technology development has made it possible to design and manufacture Integrated Circuits (ICs) where complete systems are placed on single dies; so called system chips. Manufacturing these advanced system chips is complex and cost of test increases; test cost does not directly scale with transistor count, dies size, device pin count, or process technology. A major obstacle is the increasing test data volume, which leads to problems with low throughput, long test application times and high Automatic Test Equipment (ATE) memory requirements. These problems have been addressed separately by multi-site test to improve the throughput, abort-on fail test to reduce the test time, and test data compression to reduce the ATE memory requirement. This talk will first discuss why these problems should be addressed in an integrated manner and then introduce a scheme for combined abort-on-fail testing, multi-site test and test data compression.
BIOGRAPHY:
Erik Larsson is Associate Professor (Docent) at the Department of Computer and Information Science at Linkopings Universitet. He received his M.Sc., Tech. Lic and Ph.D from Linkoping University in 1994, 1998, 2000, respectively. From October 2001 to December 2002 he was at a Japan Society for the Promotion of Science (JSPS) funded Post Doc position at the Computer Design and Test Laboratory at Nara Institute of Science and Technology (NAIST), Nara, Japan.
His current research interests include the development of tools and design for testability methodologies to facilitate the testing of complex digital systems. The main focuses are on system-on-chip test scheduling and test infrastructure design (more information can be found at SOC Test Site).
He is author of the book Introduction to Advanced System-on-Chip Test Design and Optimization (Springer 2005) and co-guest editor for the IEE Computers & Digital Techniques special issue on "Resource-Constrained Testing of System Chips". He received the best paper award for the paper "Integrated Test Scheduling, Test Parallelization and TAM Design" at IEEE Asian Test Symposium (ATS), 2002.
Enquiries: Miss Temmy So at tel 2609 8444
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar