Title:	Review of VLSI Floorplan Representations
Date:	September 6, 2006 (Wednesday)
Time:	4:30 p.m. - 5:30 p.m.
Venue:	Room 121, 1/F, Ho Sin-hang Engineering Building, The Chinese University of Hong Kong, Shatin, N.T.
Speaker:	Professor C.K. Cheng Department of Computer Science and Engineering University of California USA

ABSTRACT:

We classify VLSI floorplan representations into two categories: graph based and placement based models. The graph based models include constraint graphs, corner stitching, twin binary tree, and O-tree. These representations adopt constraint graphs as a basic structure and derive reduced versions to simplify the encoding. The corner stitching extracts the constraint graph by recording only the four neighboring blocks to each block. The twin binary tree then reduces the information to only two neighbors of each block and organizes the neighborhood relations in a pair of binary trees. The O-tree is a further simplification to the twin binary tree. It keeps only one tree for encoding.

The placement based representations use the relative positions between blocks in a placement for encoding. This category includes sequence pair, bounded sliceline grid, corner block list, and slicing trees. The sequence pair and bounded sliceline grid can be applied to general floorplan. The corner block list records only the relative position of adjacent blocks and is available for mosaic floorplans only. The slicing trees are for slicing floorplans, which are a type of mosaic floorplans. The slicing floorplans can be constructed by hierarchical horizontal or vertical merges and thus can be captured by a binary tree structure known as the slicing trees.

BIOGRAPHY:

Professor C.K. Cheng is currently a professor at the Department of Computer Science and Engineering in the University of California, San Diego, and is an Adjunct Professor at the Department of Electrical and Computer Engineering in the same university. He is also an Honorary Guest Professor at the Department of Computer in Tsinghua University from 2002-08. He has served as a Senior Engineer, Chief Scientist, and Consultant at various System, Design, and Electronic Design Automation Companies. He got his Ph.D. from the Department of Electrical Engineering and Computer Science at the University of California, Berkeley in 1984. He received the IEEE Circuits and Systems Society, CAD Transaction Best Paper Award in 1995 and 2001, the IEEE Fellow in 2000 and the IBM Faculty Award in 2004.

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