Title:	Re-synthesis for Delay Variation Tolerance
Date:	June 23, 2006 (Friday)
Time:	10:00 a.m. - 11:00 a.m.
Venue:	Room 1021, 10/F, Ho Sin-hang Engineering Building, The Chinese University of Hong Kong, Shatin, N.T.
Speaker:	Professor Shih-Chieh Chang Vice-Chair Department of Computer Science and Information Engineering National Tsing-Hua University Taiwan

ABSTRACT:

Several factors such as process variation, noises, and delay defects can degrade the eliabilities of a circuit. Traditional methods add a pessimistic timing margin to resolve delay variation problems. In this paper, instead of sacrificing the performance, we propose a re-synthesis technique which adds redundant logics to protect the performance. Because nodes in the critical paths have zero slacks and are vulnerable to delay variation, we formulate the problem of tolerating delay variation to be the problem of increasing the slacks of nodes. Our re-synthesis technique can increase the slacks of all nodes or wires to be larger than a pre-determined value. Our experimental results show that additional area penalty is around 21% for 10% of delay variation tolerance.

BIOGRAPHY:

Prof. Shih-Chieh Chang received the B.S. degree in Electrical Engineering from National Taiwan University in 1987 and the Ph.D. degree in Electrical Engineering from the University of California, Santa Barbara in 1994. He worked at Synopsys, Inc. in Mountain view, CA, from 1995 to 1996. Then, He joined the faculty at the Department of Computer Science and Information Engineering of National Chung Cheng University from 1996-2001. He is now a professor and vice chairman in the Department of Computer Science of National Tsing-Hua University. His current research interests include logic synthesis, Functional Verification for SoC, and Noise Analysis. He received a Best Paper award at the 1994 Design Automation Conference.

Enquiries: Miss Temmy So at tel 2609 8444

For more information, please refer to http://www.cse.cuhk.edu.hk/seminar