CEG3470 Digital Circuits

Lecture Notes

• Week 1 (1/9/08) - Introduction (intro and chap1)
• Week 2 - Manufacturing (ppt)
• Week 3-4 - Devices (ppt and ppt)
• Week 5 - Wire (ppt)
• Week 6-7 - The Inverter (ppt). Here are machines copies of notes handed out in lectures on buffer sizing and minimising energy. Also see these revision slides.
• Week 8-10 - Combinational Logic (ppt).
• Week 11-12 - Sequential Circuits (ppt).
• Week 13 - Logical Effort (ppt).

Midterm

• The midterm will be held on Mon 3rd Nov 2008
• 2004 midterm exam (note that the course contents were different that year).
• 2007 midterm exam. 11:50am 27/10/08 - some inaccuracies in the solution to Q2 were corrected.

Final

• Here is a sample final exam (2004) (pdf).
• Here is another sample final exam with solutions (2007) (pdf).

Field Trip

• For those participating in the field trip to the Intel Application Center, Shenzhen, we will meet at the University train station (ticket counter side) at 1:45pm. Bring enough RMB to purchase your own mainland subway ticket and don't forget your travel documents. PLEASE BE PUNCTUAL, WE WILL NOT BUY TICKETS FOR PEOPLE THAT ARE LATE.

Tutorials

• Tutorials will be held during period M5 (Mon 12:30pm) in HYS303. There are no tutorials in the first week.
• Refer to the tutorial WWW page

Useful Tools

• Spreadsheet for calculating transistor drain current.

Other Links

• Slides from book (link)
• Website for the other reference textbook, CMOS VLSI Design A Circuits and Systems Perspective by Weste and Harris (link).
• Link to last year's course (link)
• An example of a modern chip is the 6 core Intel Xeon Dunnington which has 1.9 billion transistors in 45nm technology. Here is a photo of the 300mm wafer and a press release. A 45nm fab costs about US$3B to build. See this Fab 32 tour.
• MOS Transistor simulation (link)
• Report describing the Berkeley Spice level 1-3 models (link)