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A Compiler for High Performance Computing on Array Technologies

Overview

The new multi-core, reconfigurable computing and graphics processing unit technologies, referred to as "array technologies" (AT), offer improved price and performance over conventional high performance computers (HPC). They can often sustain higher numbers of floating point operations per second as they are more specialized than traditional processors, and are widely regarded as an important direction for HPCs.

The main barrier for the adoption of array technologies is that even for experts, they are difficult to program. Since decades of compiler research has not resulted in a general solution, we limit our study to a class of financial engineering and optimization applications. We aim to develop methodologies and tools for for the utilization of ATs. The resulting tool can be used in applications including derivative pricing, risk management, portfolio optimization, time series prediction and enterprise resource management. We hope that this work will lower the barrier for entry both in terms of price-performance and user-friendliness and enable the widespread use of array technologies.

Acknowledgement

We gratefully acknowledge the support of Cluster Technology and the Hong Kong Innovation and Technology Commission through grant number ITS/027/07, "A Compiler for High Performance Computing on Array Technologies".

What's  New

• Launched project website - November 7, 2007
• The paper "Map-reduce as a Programming Model for Custom Computing Machines" was will be presented at the FCCM 2008 Conference (more ...) - February 27,2008

Key Milestones

• more ...