CENG3430 Rapid Prototyping of Digital Systems (Spring 2020)

Course Information

Lecture Time and Place	MON 16:30~18:15 (@ ERB 404) (ZOOM)
Lab Time and Place	TUE 16:30~18:15 (@ SHB 102) (ZOOM)
Course Instructor / Consultation Hours	*Prof. Ming-Chang YANG / requested by email* @ SHB 906**
Teaching Assistants / TA Hours	Tinghuan CHEN / FRI 13:30~15:00 @ SHB 905 / thchen@cse.cuhk.edu.hk (ZOOM) Guangliang YAO / FRI 13:30~15:30 @ SHB 1026 / glyao@cse.cuhk.edu.hk (ZOOM)

Announcements

May 11, 2020: The submission deadline of final project is further extended to 11:59pm on May 26, 2020.
~~Apr. 30, 2020: The submission deadline of final project is extended to 11:59pm on May 19, 2020~~.
Apr. 30, 2020: The scores of lab exercises are posted. Please contact us by 11:59pm on May 8, 2020 if you have any questions.
Apr. 27, 2020: The schedule of final project progress report & consultation is updated. (ZOOM)
Apr. 21, 2020: The course schedule is revised and posted. (ZOOM)
Apr. 14, 2020: The presentation schedule of final project proposal is posted.
Mar. 24, 2020: The specification of final project is posted (submission deadline: 11:59pm on April 13, 2020 via blackboard). (ZOOM)
Feb. 18, 2020: To better prepare the hardware materials for you, please complete this questionnaire by 06:15pm on 18 Feb., 2020.
Feb. 16, 2020: The special arrangements for online teaching are posted (password will be sent out via blackboard email).
Feb. 14, 2020: CUHK announces that online teaching for Term 2 will begin on 17 February as scheduled.
Jan. 25, 2020: CUHK announces classes will resume on February 17.
Jan. 6, 2020: Course webpage is built up and the teaching schedule is online.

Lecture and Lab

Week No.	Lecture	Lab
Week 1	Jan. 6 (Mon) Lecture 00: Course Information Lecture 01: Introduction to VHDL	Jan. 7 (Tue) No LAB Note: No tutorial will be held for the first week.
Week 2	Jan. 13 (Mon) Lecture 01: Introduction to VHDL (Cont'd)	Jan. 14 (Tue) Lab 01: Introduction to Vivado & Software Simulation
Week 3	Jan. 20 (Mon) Lecture 02: Introduction to ZedBoard Lecture 03: Architectural Styles of VHDL	Jan. 21 (Tue) Lab 02: First Program on ZedBoard
Week 4	Jan. 27 (Mon) Lunar New Year Vacation (NO LECTURE)	Jan. 28 (Tue) Lunar New Year Vacation (NO LECTURE)
	Feb. 3 (Mon) CUHK announces classes will resume on February 17.	Feb. 4 (Tue) CUHK announces classes will resume on February 17.
	Feb. 10 (Mon) CUHK announces classes will resume on February 17.	Feb. 11 (Tue) CUHK announces classes will resume on February 17.
Week 5	Feb. 17 (Mon) Lecture 03: Architectural Styles of VHDL (Cont'd)	Feb. 18 (Tue) Lab 03: 4-to -1 Multiplexer1 Multiplexer
Week 6	Feb. 24 (Mon) Lecture 04: Combinational Circuit and Sequential Circuit	Feb. 25 (Tue) Lab 04: Serial-In-Parallel-Out Shift Register
Week 7	Mar. 2 (Mon) Lecture 05: Finite State Machine Lecture 06: Use of Clock Sources and Peripheral Modules on ZedBoard	Mar. 3 (Tue) Lab 05: Driving the Seven Segment Display
Week 8	Mar. 9 (Mon) Lecture 07: Driving VGA Display with ZedBoard Lecture 08: Use of Signals and Variables	Mar. 10 (Tue) Lab 06: Driving the VGA Display
Week 9	Mar. 16 (Mon) Lecture 08: Use of Signals and Variables (Cont'd)	Mar. 17 (Tue) Lab 07: Software Stopwatch
Week 10	Mar. 23 (Mon) Lecture 09: Rapid Prototyping (I) - Integration of ARM and FPGA (Cont'd)	Mar. 24 (Tue) Lab 08: Software Stopwatch with Embedded Linux
Week 11	Mar. 30 (Mon) Reading Week (NO LECTURE)	Mar. 31 (Tue) Reading Week (NO LECTURE)
Week 12	Apr. 6 (Mon) Lecture 11: Rapid Prototyping (III) - High Level Synthesis	Apr. 7 (Tue) Lab 09: Accelerating Floating Point Matrix Multiplication with High-Level Synthesis
Week 13	Apr. 13 (Mon) Public holiday – Easter (NO LECTURE)	Apr. 14 (Tue) Final Project Proposal Presentation
Week 14	Apr. 20 (Mon) Lecture 12: VHDL versus Verilog	Apr. 21 (Tue) Lab 10: Serial-In-Parallel-Out Shift Register in Verilog
Week 15	Apr. 27 (Mon) Final Project Progress Report & Consultation	Apr. 28 (Tue) Final Project Progress Report & Consultation

References

VHDL for Programmable Logic, Kevin Skahill, Addison-Wesley.
Digital Systems Design Using VHDL, Charles H. Roth Jr., and Lizy Kurian John, Cengage Learning.
The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc, Louise H Crockett, Ross A Elliot, Martin A Enderwitz, and Robert W Stewart, Strathclyde Academic Media.
The Zynq Book: Tutorials for Zybo and ZedBoard, Louise H Crockett, Ross A Elliot, and Martin A Enderwitz, Strathclyde Academic Media.