CENG3430 Rapid Prototyping of Digital Systems (Spring 2019)

Course Information

Lecture Time and Place	MON 16:30~18:15 (@ ERB 404)
Lab Time and Place	TUE 16:30~18:15 (@ SHB 102)
Course Instructor / Consultation Hours	Prof. Ming-Chang YANG / TUE 14:00~16:00 @ SHB 906
Teaching Assistants / TA Hours	Zhiliang ZENG / FRI 15:30~17:30 @ SHB 902 / zlzeng@cse.cuhk.edu.hk Tinghuan CHEN / FRI 14:00~16:00 @ SHB 905 / thchen@cse.cuhk.edu.hk

Announcements

Lecture and Lab

Week No.	Lecture	Lab
Week 1	Jan. 7 (Mon) Lecture 00: Course Information Lecture 01: Introduction to VHDL	Jan. 8 (Tue) NO LAB
Week 2	Jan. 14 (Mon) Lecture 01: Introduction to VHDL (Cont'd)	Jan. 15 (Tue) Lab 01: Introduction to Vivado & Behavioral Simulation
Week 3	Jan. 21 (Mon) Lecture 01: Introduction to VHDL (Cont'd) Lecture 02: Introduction to ZedBoard	Jan. 22 (Tue) Lab 02: First VHDL Program on ZedBoard
Week 4	Jan. 28 (Mon) Lecture 03: Architectural Styles of VHDL	Jan. 29 (Tue) Lab 03: Tri-state Logic and Resolved Logic
Week 5	Feb. 4 (Mon) Lunar New Year Vacation (NO LECTURE)	Feb. 5 (Tue) Lunar New Year Vacation (NO LAB)
Week 6	Feb. 11 (Mon) Lecture 04: Building Blocks of a Processor	Feb. 12 (Tue) Lab 04: 4-to-1 Multiplexer
Week 7	Feb. 18 (Mon) Lecture 05: Finite State Machine	Feb. 19 (Tue) Lab 05: Serial-in-parallel-out Shift Register
Week 8	Feb. 25 (Mon) Lecture 05: Finite State Machine Lecture 06: Use of Clock Sources and Peripheral Modules on ZedBoard	Feb. 26 (Tue) Lab 06: Driving Pmod Seven Segment Display
Week 9	Mar. 4 (Mon) Lecture 05: Finite State Machine	Mar. 5 (Tue) Lab 07: Driving VGA Display
Week 10	Mar. 11 (Mon) Lecture 05: Finite State Machine Lecture 07: Rapid Prototyping (I) - Integration of ARM and FPGA Final Project Specification	Mar. 12 (Tue) Lab 08: Software Stopwatch Using ARM & FPGA
Week 11	Mar. 18 (Mon) Lecture 07: Rapid Prototyping (I) - Integration of ARM and FPGA Lecture 08: Rapid Prototyping (II) - Embedded Operating System	Mar. 19 (Tue) Lab 09: Software Stopwatch with Embedded Linux
Week 12	Mar. 25 (Mon) Final Project Proposal Presentation	Mar. 26 (Tue) Lab 10: High Level Synthesis Exercise Final Project Proposal Feedback
Week 13	Apr. 1 (Mon) Reading Week (NO LECTURE)	Apr. 2 (Tue) Reading Week (NO LAB)
Week 14	Apr. 8 (Mon) Lecture 10: VHDL versus Verilog	Apr. 9 (Tue) Lab 11: Verilog Exercise: Serial-in-parallel-out Shift Register Final Project Progress Report
Week 15	Apr. 15 (Mon) Lecture 09: Rapid Prototyping (III) - High Level Synthesis	Apr. 16 (Tue) Final Project Demonstration

References

• VHDL for Programmable Logic, Kevin Skahill, Addison-Wesley.
  
• Digital Systems Design Using VHDL, Charles H. Roth Jr., and Lizy Kurian John, Cengage Learning.
  
• The Zynq Book: Embedded Processing with the Arm Cortex-A9 on the Xilinx Zynq-7000 All Programmable Soc, Louise H Crockett, Ross A Elliot, Martin A Enderwitz, and Robert W Stewart, Strathclyde Academic Media.
  
• The Zynq Book: Tutorials for Zybo and ZedBoard, Louise H Crockett, Ross A Elliot, and Martin A Enderwitz, Strathclyde Academic Media.