Voltage Island Generation
Energy efficiency has become one of the most important issues to be
addressed in today's System-on-a-Chip (SoC) designs because of the
increasing power density and the wide use of portable systems.
There are many techniques to reduce power consumption. One of the most
effective methods is by lowering the voltage supply.
Multi-voltage design is thus introduced to
provide "just enough" power to support different functional operations.
Both dynamic and leakage power consumption can be reduced in multi-voltage
designs. For dynamic power, since the consumption is proportional to the
square of the voltage, a minor adjustment to the voltage level can result
in a significant reduction. For leakage power, the consumption can be reduced
by powering down parts of a chip when the functions are inactive.
Multi-voltage designs involve the partitioning of a chip into
areas called "voltage islands" that can be operated
at different voltage levels,
or be turned off when idle. With the use of voltage islands, the chip
design process is becoming more complicated.
We need to solve the problems of island partitioning,
voltage assignment and floorplanning under area,
power, timing and other physical constraints.
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Publications:
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Network Flow Based Power Optimization under
Timing Constraints in MSV-driven Floorplanning,
Qiang Ma and Evangeline F.Y. Young,
Proceedings IEEE International Conference on Computer-Aided Design, 2008.
(executables and data)
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Voltage Island-Driven Floorplanning,
Qiang Ma and Evangeline F.Y. Young,
Proceedings IEEE International Conference on Computer-Aided Design, 2007.
(executables and data)
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Post-placement Voltage Island Generation,
Royce L.S. Ching, Evangeline F.Y. Young and Chris Chu,
Proceedings IEEE International Conference on Computer-Aided Design, 2006.
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People:
- Qian Zaichen, Aaron (MPhil)
- Ma Qiang, Marvin (MPhil)
- Ching Lap Sze, Royce (MPhil)
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Funding:
- RGC Earmarked Grant on "Voltage Island Partitioning and Floorplanning" (2007-09)