Ripple: Routability-Driven Placer

Routability has become an important issue in VLSI physical design. Placement plays an important role in physical design and can affect significantly the quality of the routing solution. In most previous placers, the major objective is to minimize wirelength which is often estimated by the half-perimeter wirelength (HPWL) model. Although minimizing HPWL can reduce the average routing demand, the routing demand may be distributed unevenly and as a result, some nets are difficult to be routed or even unroutable at the end. Moreover, hundreds of large macros which occupy several metal layers usually exist and their existence have made routing even more challenging. We have developed a routability-driven placer called Ripple. New techniques have been explored to understand how routability can be improved through placement.