Interconnect Prediction
Interconnect prediction in floorplanning is a step to guess how well a floorplan
design will be in terms of routability. This is an important task in this
deep submicron era when the complexity of circuit design is skyhigh and interconnect
delay has dominated gate delay. This is not an easy task as
routing is not done yet and there are a huge number of interconnects running between
the modules. In order to tackle this challenging problem, we have tried different
approaches. The paper [3,4,5] are our previous works on this problem using probabilistic
approach. The work in [4] is the most sophisticated one among the three in terms of theory
and mathematical derivation, etc. but the performance of [3] is the best. The approach
in [3] is simply placing buffers greedily first using dynamic programming and then
estimating congestion between buffer/gate and buffer/gate assuming shortest
Manhattan multibend routes. The approach in [2] is totally different. A term wire
density is defined which is related to congestion indirectly. By using the
twin binary tree floorplan representation, wire density can be computed
effectively. The approach in [2] can be used to predict congestion quickly but
the accuracy may not be as good as that in [3,4,5].
Our most recent work is presented in [1]. This is also a probabilistic approach
considering important routing details like bending, ripupandreroute, detours, etc.
The prediction accuracy is found to be obviously improved with such details taken
into account.

Publications:

[1] Congestion Prediction in Early Stages,
Chiuwing Sham and Evangeline F.Y. Young,
International Workshop on SystemLevel Interconnect Prediction, pp.9198, 2005.

[2] A New and Efficient Congestion Evaluation Model in
Floorplanning: Wire Density Control with Twin Binary Trees,
Steve T.W. Lai, Evangeline F.Y. Young and Chris C.N. Chu,
Proceedings of Design, Automation and Test in Europe, 2003.

[3] Fast Buffer Planning and Congestion Optimization in
Interconnectdriven Floorplanning,
Keith K.C. Wong and Evangeline F.Y. Young,
IEEE Asia South Pacific Design Automation Conference, pp.411416, 2003.
Candidates for Best Paper Award (12 out of 235).

[4] Routability Driven Floorplanner with Buffer Block
Planning,
C.W. Sham and Evangeline F.Y. Young,
International Symposium on Physical Design, pp.5055, 2002.

[5] Congestion Estimation with Buffer Planning in
Floorplan Design,
C.W. Sham, W.C. Wong and Evangeline F.Y. Young,
Proceedings of Design, Automation and Test in Europe, pp.696701, 2002.

People:

Funding:
 RGC Earmarked Grant on "InterconnectDriven Multilevel Floorplan Design" (200104)