Interconnect Prediction

Interconnect prediction in floorplanning is a step to guess how well a floorplan design will be in terms of routability. This is an important task in this deep submicron era when the complexity of circuit design is sky-high and interconnect delay has dominated gate delay. This is not an easy task as routing is not done yet and there are a huge number of interconnects running between the modules. In order to tackle this challenging problem, we have tried different approaches. The paper [3,4,5] are our previous works on this problem using probabilistic approach. The work in [4] is the most sophisticated one among the three in terms of theory and mathematical derivation, etc. but the performance of [3] is the best. The approach in [3] is simply placing buffers greedily first using dynamic programming and then estimating congestion between buffer/gate and buffer/gate assuming shortest Manhattan multi-bend routes. The approach in [2] is totally different. A term wire density is defined which is related to congestion indirectly. By using the twin binary tree floorplan representation, wire density can be computed effectively. The approach in [2] can be used to predict congestion quickly but the accuracy may not be as good as that in [3,4,5]. Our most recent work is presented in [1]. This is also a probabilistic approach considering important routing details like bending, rip-up-and-reroute, detours, etc. The prediction accuracy is found to be obviously improved with such details taken into account.