Analog Placement

In today's SoC designs, both digital and analog parts of a circuit will be implemented on one chip. Placement of the analog parts is an error prone and time-consuming process. In analog placement, parasitic mismatch induced by the layout will affect the circuit performance significantly. One of the most important sources of mismatch is process gradient, like oxide thickness, threshold voltage, resistor-layer thickness, etc. These kinds of mismatch can be effectively suppressed by common centroid layout, which refers to a layout style in which a set of devices have a common center point. Devices will be split into a number of smaller ones and placed with the same center point. The devices can be arranged in one dimension or in two dimensions. Two-dimensional arrangement is desired especially when the number of devices is large, since close proximity is desirable for better electrical properties such as parasitic matching and thermal gradients. Considerations of symmetry constraints during placement, in which pairs of cells are required to be placed symmetrically with respect to a horizontal or vertical axis, can also help to reduce those errors.