CEG5010 Reconfigurable Computing

Assignment (10%)

Electronic submission guideline (Tutorial 3 and 4)

uuencode loginname.tar.gz loginname.tar.gz | elm -s "Assignment #" ceg5010

If you have not used 'elm' before, please invoke the program once before submit your files using the above command.
Replace with your own login name (loginname) and the corresponding assignment number (#).
You will receive an auto-reply from the system.
For students in other departments, please contact the tutors individually.

Tutorial 1: Virtex-II Architecture (1) (2%)

1. How many Virtex-II slices do you need to implement a 4:1 MUX? Show your implementation using a diagram.
2. With diagrams, show how to implement a 24-bit shift register using the minimum number of Virtex-II slices. Remember to show your configurations to the slices whenever necessary.
3. Suppose you want to implement the Boolean function F = abx' + cdx' + efgx + hx using Virtex-II slices, how many slices do you need? Explain your implementation.

Tutorial 2: Virtex-II Architecture (2) (2%)

1. Discuss the differences between Block SelectRAM and Distributed SelectRAM (in 300-500 words).
2. Write VHDL/Verilog code to implement a 52-bit LFSR as described in the application note xapp210.

Tutorial 3: Core Simulation (3%)

Objective: To bulid a Greatest Common Divider (GCD) Core for simulation
Deadline: 28/1/2008 3:30 p.m.
Specification:

• You are required to construct a GCD using VHDL. The core should be able to generate the GCD of two numbers.
• Input A and B are 8-bit unsigned integers. The output D is a 8-bit unsigned integer where D=GCD(A,B).
• After receiving a RUN signal, the circuit samples the inputs and start computing. After (or maybe at the same time) the correct GCD is computed , the RDY signal asserts and the output is ready.
• You can assume that A and B are non-zero.
• The entity of the core is given in the resource part below. No modification of the entity is allowed. Your design should be in pure VHDL(Verilog) which can be simulated in Xilinx ISE. Although you can use some non-synthesizable VHDL constructs, this may post problems later.
• You must hand in the following files:
  gcd_tb.vhd: the testbench for simulation the core.
  gcd_core.vhd: the main core of GCD.
  *.vhd: any other VHDL source files used in the design.
• Sample VHDL entity declaration:
  

  entity gcd_core is
  port (
  	CLK:	in	std_logic;
  	RST:	in	std_logic;
  	RUN:	in	std_logic;
  	A:	in	std_logic_vector(7 downto 0);
  	B:	in	std_logic_vector(7 downto 0);
  	RDY:	out	std_logic;
  	D:	out	std_logic_vector(7 downto 0)
  );
  end gcd_core;

• CLK: the input clock signal (20 MHz; 50% duty cycle)
  RST: synchronous global rese input, the FSM starts working after rst goes low, FSM halts and reinitializes when rst up again
  RUN: last exactly one clock cycle, trigger the core to run
  A, B: input numbers
  RDY: signal the external world that the result is computed and outputted, at least last one clock cycle but can last as long as the output is valid
  D: the output generated by the GCD

Tutorial 4: Interface Design (3%)

• (FPGA side) Design an interface between the ARM processor and the FPGA such that the ARM processor can control the GCD core implemented on the FPGA.
• Write VHDL / Verilog code for the interface circuit. Embed your core inside the interface.
• (ARM Side) Develop a user program on the ARM processor to test the GCD core.
• No calculation related to the GCD is allowed on the ARM program.
• Test the core with at least 3 pairs of numbers and find their GCD using the GCD core. You may be asked to modify the test pair during demo.
• You are expected to poll the RDY signal to make sure the core had finished the previous calculation before you start the next calculation.