CEG3490 VLSI Systems

• Reminder:
  • Final class and presentation: 14/5 (Wednesday) 1:30pm - 4:15 pm, room SHB504 (NO class on 11/4, 15/4)
  • Final layout submission: 12/5 (Monday) 11:59 pm
  • Project demo schedule: 13/5 (Tuesday) starting from 2:00pm (see this)
• 14/04/2008: Test cases for the project has been released.
  15/04/2008: Suggested solution for quiz posted.
• 02/04/2008: Tutorial 9 posted. (updated on 3/4)
  28/03/2008: Midterm suggested solution posted.
  28/03/2008: Homework 5 has been released.
• 14/03/2008: Homework 4 has been modified. (Q2d, Q5)
  14/03/2008: Solutions for Homework 4 Similar Questions have been bug-fixed(Q2b).
• 11/03/2008: There are some modifications for Homework 4.
• 11/03/2008: Homework 4 is out.
• 10/03/2008: Sample layout for Homework 2 Q1 is available.
  
• 02/03/2008: Homework 3 postponed for two days. New deadline: 05/03/2008 23:59.
  
• 01/03/2008: Suggested solution for Homework 1 is ready.
• 01/03/2008: mpla template updated.
• 21/02/2008: Project specification is now available.
• 18/02/2008: Homework 3 is out. The deadline is 1:30pm 3 March, 2008
• 15/02/2008: Tutorial note 5 and layout examples were posted.
• 05/02/2008: Notes for Chapter 12, 13, 14 are out.
• 01/02/2008: Domino AND gate example in tutorial 3 and tutorial note 4 is posted.
• 31/01/2008: Homework 2 is out. The deadline is 6:00pm 15 Feb, 2008.
• 30/01/2008: Chapter 5-11 are now available.
• 25/01/2008: Magic example in tutorial 2 and tutorial note 3 is posted.
• 20/01/2008: Homework 1 is posted. The deadline is 6:30pm 1st Feb, 2008.
• 18/01/2008: Homework 0 (self-practice) is posted. Take the chance to revise and practise your layout techniques.
• 10/01/2008: Tutorial 1 will be held on 18/1 (F6). Venue: ERB 408. Official layout tools package is posted.
• 08/01/2008: Chapter 2, 3, 4 are available

Textbook

• (Majorly) class handouts (Word/ps files are available at course webpage)
• "Modern VLSI Design - System-On-Chip Design" by Wayne Wolf, 3rd Edition, (Publisher: Prentice Hall)
• (Reference) "Essentials of Electronic Testing for Digital, Memory & Mixed-Signal VLSI Circuits" by M. L. Bushnell, V. D. Agrawal (Publisher: KAP)
• (Reference) "Principles of CMOS VLSI Design" by Neil H.E., Weste and Kamran Eshraghain (Publisher: Addison-Wesley)

Syllabus

This is an introductory level course trying to wrap up a wide coverage of fundamentals from several areas, which should be useful for a CE student both for further graduate study or practical industry applying. High light of the coverage would be:

• Design, analyzing for VLSI circuits, building the capability of low-level manual layout from components to a whole chip system involving I/O pads, data-path, clocking schemes, sequential logic, control logic, and switch level simulation.
• Related knowledge: charge sharing, static/dynamic logic, CMOS/NMOS designs.
• Circuit performance, power, delay calculation (tau-model, Elmore delay)
• Retiming technique for sequential circuits.
• Hardware Testing fundamentals (stuck-at fault model, ATPG,..)
• State-of-the-art Circuit Rewiring technique (not in any textbook) and logic optimization applications.
• Regular Fabrics
• Whole chip design project (2~3 person group)
• Asynchronopus cirucits, harzard-free design (optional)
• Design for Manufacturability (DFM) (optional)

Note:
The major vision of this class is to guide the students master the most basic and useful concept/skills on the VLSI manual designs, CAD and testing techniques. The project work forms the corner stone of this effort. Students are expected to work on a sizable team work project, doing an effective project presentation, and wrapping up a well-organized group report. You must work on the homework alone and without any unauthorized person's assistance. The efforts spent on homework will be directly reflected in the exam performance. Plagiarism caught will fail this course automatically and be reported to the Department Discipline Committee. Late homework penalty will be 10% per day. No make-up exams. In case of significant medical reasons, scores will be made proportionally based on other scores.

Academic layout tools: MAGIC

Official layout tool: magic 7.1.3 | Technology: AMI 0.5u
Homepage: Magic VLSI Layout Tool | Old Page
Tarball: magic-7.1.3-tarball.tar.gz contains

• magic 7.1.3 system files and binary exectuables
• Technology files and parameter files for layout and simulation
• Sample layout (inverter) and Makefile for simulation

Utilities:

• Makefile
• 0.5um parameter file for IRSIM
• mpla template for 0.5um technology (put in $MAGIC/lib/mpla)
• bash script to get the size
• bash script to extract and simulate
• IO PAD for 0.5um technology

Installation Guide (Fedore Core Linux >= 4)

1. unzip the tarball: $ tar zxvf magic-7.1.3-tarball.tar.gz
2. add the line "export CAD_HOME=$HOME/magic-7.1.3" to your .bashrc
3. add the line "export PATH=$PATH:$HOME/magic-7.1.3/bin" to your .bashrc
4. add the line "alias magic='magic -T SCN3M_SUBM.30'" to your .bashrc
5. don't forget to refresh the environment: $ source .bashrc

Homework

• Homework 0: (self-practice) PS PDF xor.jpg
• Homework 1: PDF · Sample Layout · Layout Size Stat · Suggested solution
• Homework 2: PDF · Layout Size Stat · Sample layout for Q1 · Screenshot of the sample layout for Q1 · Suggested solution
• Homework 3: PDF
• Homework 4: PDF(last updated on 14/03/2008) · Similar Questions · Suggested solution for the Similar Questions(last updated on 14/03/2008)
• Homework 5: PDF · Suggested solution

Submission

What you should submit for homework?

• Unless otherwise stated, you need to submit both soft copy and hard copy of the layout and simulation result.

How to submit homework (soft copy)?

• ZIP all your MAGIC & IRSIM files (.mag, .cmd) with your username (e.g. tmchan) using:
  

  gtar zcvf tmchan.tar.gz *.mag *.cmd

• Submit it use the following command:
  

  uuencode tmchan.tar.gz tmchan.tar.gz | elm -s "Homework ?" ceg3490

• Please noted that the subject must be "Homework ?" (with double quotes), for example "Homework 3".
  And the filename must be [username].tar.gz.
• You will receive auto-reply email. Check if your attachement is empty or not. Keep the auto-reply until the end of our course.

Course Project

• Project Specification: PDF
• Example MAGIC components: fpga-example-components.tar.gz
• Test cases: PDF

Submission

How to submit project (soft copy)?

• Choose one group member to submit your project
• ZIP all your MAGIC & IRSIM files (.mag, .cmd) and other related files with the username of the chosen member (e.g. tmchan) using:
  

  gtar zcvf tmchan.tar.gz *.mag *.cmd

• Submit it use the following command:
  

  uuencode tmchan.tar.gz tmchan.tar.gz | elm -s "Homework Phase?" ceg3490

  Remember to replace ? with your submission no.