Tutorial 3 posted

You can get the tutorial note here: Download
The technology files are here: Download.

Lecture note 8 posted

This version is stable. You can Download and print the slides.

Suggested Solution For HW 1 Posted

Here is link of suggested solution for HW1.

Lab 2 Posted

This is another drill on your combinational circuit design and layout technique. A 1-bit FA adder has to be drawn and simulated. Get It

Reference Answer for Tutorial 3

Reference answer for tutorial 3 has been uploaded. link

Lecture note 5 updated

As I said during lectures, I have added back the sizing formula to lecture note 5. Please update your copies. Page 23, 24, 36 and 37 are added/updated.

Tutorial 3 for Midterm Revision.

Harry is going to explain questions related to logical effort calculations. Please try to attend.

Lecture 7 posted extended.

I have added pages 27 to 39 discussing MOS cap. Please update your copy.
We will study carefully about the MOS transistor and derive its characteristic equations. You can download the note here.

Secret Cell pictures available.

We had a wonderful evening with these two PROFESSIONAL layouts extracted from the standard cell library. Give a try to strengthen your layout reading technique. I will give you the answer next Monday during lecture. Cell A · Cell B

Lecture 6 posted.

We will start the discussion on memory decoder after we finish the revision exercise. Download

HW 1 posted.

We are going to practise hand calculations for combinational circuit optimization. Please revise chapter 3 and 4 while doing HW 1. Download

Tutorial note 2 posted.

You can get the note from the tutorial page or here

Revision Exercise for Ch. 4 & 5 posted.

We go through question 1 today. Please try question 2 during the week and we are going to explain next Monday. Download

Lecture 5 posted updated.

Please refresh your copies.
You can get note here [lec05.ppt]. Please be prepared to copy some examples to be discussed on the whiteboard in addition to the notes.

Lab 1 posted.

The first practical exercise is released. You have 1 week to layout a 4-input cell with a Boolean function generated based on your student ID. More details at HW/Lab page, or you can get the spec directly.

Tutorial 1 posted.

The first tutorial will discuss the usage of MAGIC. Please attend since the tool will be used for the whole semester. You can get the tutorial note here

Lecture 4 posted.

You can get the latest version here [lec04.ppt]

Revision Exercise (Layout Colouring) posted.

This exercise would help you to understand the material in lecture note 3. Please try it before next lecture. ceg3470_layout_coloring.doc
I will conclude the exercise on Monday's lecture. Do attend.

Lecture notes 3 posted.

I will share with you a couple of videos during the lecture. Don't miss it! You can fetch the notes lec03.ppt

Lecture notes 1 posted & 2 updated.

You can fetch the notes from the Lecture Page or here. lec01.ppt & lec02.ppt

Welcome to CEG3470!

Posted by Tang Wai Chung

CEG3470 is the major required course for computer engineering majors. The course provides in-depth discussion on various issues in designing and analyzing digital circuits using CMOS technology.

In addition to theory, this course would include training to standard computer design CAD tools like MAGIC and SPICE.

This course homepage contains the supporting materials like lecture notes, tutorial notes, homework, lab handouts. Please try keeping checking for updates!

Course Information

This course examines the issues involved in designing and analysing digital circuits in CMOS technology. Topics include fabrication process, usage of SPICE, transfer characteristics, noise margin, loading effect, propagation delay, fanout analysis, transient current, power dissipation, bistable circuits and memories. A brief introduction to VLSI circuits is also included. Prerequisites: ERG2020 and ELE2110.

Staff

  Lecturer Tutor
Name Tang Wai Chung, Matthew Yu Haile
Office SHB 106 SHB 1024
Hour TBD TBD
Email

Time and Places

  • Lectures: M7-8 @ ERB703, T9 @ ERB712
  • Tutorials: W6 @ ERB712

Textbook

Digital Integrated Circuits: A Design Prespective", by Jan Rabaey, Anantha Chandrakasan and Borivoje Nikolic

References

Coming soon..

 
 
 

Assessment

Homework: 15%, Lab: 15%, Project: 15%, Mid-term: 15%, Final: 40%

Departmental Guideline for Plagiarism

If a student is found plagiarizing, his/her case will be reported to the Department Discipline Committee. If the case is proven after deliberation, the student will automatically fail the course in which he/she committed plagiarism. The definition of plagiarism includes copying of the whole or parts of written assignments, programming exercises, reports, quiz papers, mid-term examinations. The penalty will apply to both the one who copies the work and the one whose work is being copied, unless the latter can prove his/her work has been copied unwittingly. Furthermore, inclusion of others' works or results without citation in assignments and reports is also regarded as plagiarism with similar penalty to the offender.
A student caught plagiarizing during tests or examinations will be reported to the Faculty Office and appropriate disciplinary authorities for further action, in addition to failing the course.

http://www.cuhk.edu.hk/policy/academichonesty/