DAC-IOT 

International Hardware Design Contest 2017

Theme: FPGA for INTERNET-OF-THINGS

Sponsored by ACM SIGDA


Registration start date: 8:00 am PST, Nov. 16, 2016
Registration deadline: 5:00 pm PST, Jan. 15 Jan. 31, 2017 Closed
Preliminary design submission date: 5:00 pm PST, April. 15, 2017
Final design submission date: 5:00 pm PST, May. 15, 2017


The final award winners will be announced at 2017 IEEE/ACM Design Automation Conference (DAC).


Award: $2,500 for the first place team, $1,500 for second place team and $1,000 for the third place team. Up to $600 travel support will also be provided for the top five teams to attend DAC.


Registration E-mail: hdc2017contest@gmail.com


Starting this year, ACM Special Interest Group in Design Automation (SIGDA) will sponsor an annual hardware design contest with dedicated themes to boost the research and development in the related areas. For this first year, the theme is set to be FPGA for Internet-of-Things (IoT). IoT is the internetworking of physical devices, vehicles, buildings and other items-embedded with electronics, software, sensors, actuators, and network connectivity that enable these “things” to collect, exchange and operate on data. How these “things” are designed is of critical importance to the efficacy and efficiency of IoT. In this contest, we will explore the use of low-power FPGAs to implement new concepts and designs in IoT edge computing.

DESIGN RULES

  1. The contest is open equally to teams from both academia and industry. Collaborative teams between the two are also welcome.

  2. Each team is required to register (following the guidelines in the “Contest Registration” section). A brief pre-screening will be conducted and the notification of whether the registration is accepted or not will be sent out within 1 business day.

  3. Each accepted team will be provided with a Lattice FPGA board, which is required to be part of the design. Please choose one of the four boards described in BOARD CHOICE GUIDANCE section.

  4. Each team may use other components such as GPUs, CPUs, etc. if needed to form a heterogeneous system. However, we will not provide these additional components and they must be acquired at the team's own expenses.

  5. Each team may freely implement any design under the framework of IoT edge computing.

  6. As the goal of the contest is to boost the research and development of IoT, all the designs must remain open-source. After the contest, the designs will be hosted in our website for free download and use under the modified BSD license. See the Foundation for Open Source Silicon licensing page http:fossi-foundation.org/licenses.html for more details.

  7. A website will be setup for each team to post questions. These questions and answers will be visible to all participating teams. We will notify each registered team with the link to the website.

BOARD CHOICE GUIDANCE

DELIVERABLES

Each participating team should upload to the competition website a written report in PDF format with no more than 2 pages highlighting the critical components of your design, as well as a TAR.GZ archive with all developed source code and computer files. For the top five final teams selected to attend the 2017 DAC for live demos, each team should also prepare a presentation and a poster of your work. The details will be announced later.

EVALUATION CRITERIA

As this is largely an open-ended design contest, each submitted design will be evaluated by a panel of judges formed by experts from both industry and academia according to the creativity of the design. Feedback from the panel will be provided to each team. Evaluation will be a combination of positive points, awarded to the design functionality, innovation, and repeatability, easiness for implementation, robustness and security.

Specifically, positive points will be awarded based on the following criteria:

CONTEST REGISTRATION

For registration and contest related inquiries, please email: hdc2017contest@gmail.com. Please add “HDC2017” to the subject line of any email. We encourage you to register as early as possible and no later than the deadline outlined, because free FPGA boards will be limited to the first 25 teams on a first come first served basis.

To register your team, please provide the following information:

  1. Affiliation of the team/contestant(s)

  2. Names of team members

  3. One correspondence e-mail address for the team

  4. Name of the team

  5. A short paragraph of no more than 250 words about your design idea and the problem you are planning to solve.

  6. Gmail address (Technical support will be provided through Google Groups)

CONTEST ORGANIZERS:

Yiyu Shi University of Notre Dame Chair
Yier Jin University of Central Florida Co-Chair
Abdullah Raouf Lattice Semiconductor Industry Liaison
Claude Moughanni Lattice Semiconductor Industry Liaison
Bei Yu Chinese University of Hong Kong Web Support