|Registration start date:||8:00 am PST, Nov. 16, 2016|
|Registration deadline:|| 5:00 pm PST, |
|Preliminary design submission date:||5:00 pm PST, April. 15, 2017|
|Final design submission date:||5:00 pm PST, May. 15, 2017|
The final award winners will be announced at 2017 IEEE/ACM Design Automation Conference (DAC).
Award: $2,500 for the first place team, $1,500 for second place team and $1,000 for the third place team. Up to $600 travel support will also be provided for the top five teams to attend DAC.
Registration E-mail: firstname.lastname@example.org
Starting this year, ACM Special Interest Group in Design Automation (SIGDA) will sponsor an annual hardware design contest with dedicated themes to boost the research and development in the related areas. For this first year, the theme is set to be FPGA for Internet-of-Things (IoT). IoT is the internetworking of physical devices, vehicles, buildings and other items-embedded with electronics, software, sensors, actuators, and network connectivity that enable these “things” to collect, exchange and operate on data. How these “things” are designed is of critical importance to the efficacy and efficiency of IoT. In this contest, we will explore the use of low-power FPGAs to implement new concepts and designs in IoT edge computing.
The contest is open equally to teams from both academia and industry. Collaborative teams between the two are also welcome.
Each team is required to register (following the guidelines in the “Contest Registration” section). A brief pre-screening will be conducted and the notification of whether the registration is accepted or not will be sent out within 1 business day.
Each accepted team will be provided with a Lattice FPGA board, which is required to be part of the design. Please choose one of the four boards described in BOARD CHOICE GUIDANCE section.
Each team may use other components such as GPUs, CPUs, etc. if needed to form a heterogeneous system. However, we will not provide these additional components and they must be acquired at the team's own expenses.
Each team may freely implement any design under the framework of IoT edge computing.
As the goal of the contest is to boost the research and development of IoT, all the designs must remain open-source. After the contest, the designs will be hosted in our website for free download and use under the modified BSD license. See the Foundation for Open Source Silicon licensing page http:fossi-foundation.org/licenses.html for more details.
A website will be setup for each team to post questions. These questions and answers will be visible to all participating teams. We will notify each registered team with the link to the website.
Dr. Yiyu Shi will provide any one of four development boards for your demonstration. Your choice of demonstration platforms should be made according to your target application. For the sake of this contest, IoT can be identified by 1) low power battery operated applications and 2) non-battery applications.
Ultra-Low Power Battery Operated Applications
If you are targeting an extremely low power consumption application that will run from a battery, consider Lattice iCE40 devices. Lattice iCE40 FPGA devices are used in consumer mobile applications such as smartphones, remote sensors, tablets, etc. There are two development platforms to choose from. Both alternatives below come with the iCEcube development tools.
iCE40 Ultra Breakout Board
This is a simple board for evaluation and development with the iCE40 Ultra FPGA. The kit includes a PCB with an iCE40 Ultra device and power module to power the board from an AC outlet. All IOs are brought out to .100 headers for easy prototyping.
iCEstick Evaluation Kit
This is a low cost, USB form factor iCE40 evaluation board. This is super simple to utilize. You can plug this into your Windows based computer, and you are ready to go. Our iCEcube tool chain can download your compiled designs directly to the iCEstick board. If your application requires a limited number of IOs this could be your ideal choice.
IoT does not need to be ultra-low power. IoT can include applications in an automobile, or on a factory floor. An ideal choice is be the MachX03 line of FPGA devices. These FPGAs also have more flexibility in both functionality and tools (when compared to the ultra-low power iCE products). The MachX03 devices are compiled with the Lattice Diamond development tool. For these applications the following MachX03 Breakout Board is made available.
MACHXO3L Starter Kit
This MachXO3L Starter Kit board is a 3 x 3 inch form factor, and features a USB mini-B connector for power and programming, an LED array, and prototype area. It comes with a pre-loaded demonstration, a counter design that highlights use of the embedded MachXO3L oscillator and programmable I/Os configured for LED drive. A USB cable is also included with the kit, and demos area available for download. By using the free Lattice design tools, you can program the MachXO3L device to review your own custom design.
MACHXO3LF Starter Kit (w embedded Flash)
This MachXO3LF Starter Kit board is a 3 x 3 inch form factor, and features a USB mini-B connector for power and programming, an LED array, and prototype area. It comes with a pre-loaded demonstration, a counter design that highlights use of the embedded MachXO3L oscillator and programmable IOs configured for LED drive. A USB cable is also included with the kit, and demos area available for download. By using the free Lattice design tools, you can program the MachXO3L device to review your own custom design.
Each participating team should upload to the competition website a written report in PDF format with no more than 2 pages highlighting the critical components of your design, as well as a TAR.GZ archive with all developed source code and computer files. For the top five final teams selected to attend the 2017 DAC for live demos, each team should also prepare a presentation and a poster of your work. The details will be announced later.
As this is largely an open-ended design contest, each submitted design will be evaluated by a panel of judges formed by experts from both industry and academia according to the creativity of the design. Feedback from the panel will be provided to each team. Evaluation will be a combination of positive points, awarded to the design functionality, innovation, and repeatability, easiness for implementation, robustness and security.
Specifically, positive points will be awarded based on the following criteria:
The design functionality and its innovation. The whole delivered design should act as an IoT device with basic IoT functionality including wireless communication/control, information collections through sensors, mobile phone app connections, firmware upgrading capability, etc. (30%).
The easiness for implementation and repeatability. All delivered designs and source code should be self-contained so that the judges can easily reproduce the whole design for evaluation. For on-site finalists, live demos should be prepared. (30%).
Report quality and guideline completeness. All teams will submit a report along with the user guide to justify the IoT designs. The quality of the report as well as the quality of the final presentation/poster will be evaluated. (20%).
Extra properties will also be evaluated. For example, design security will be evaluated to avoid IoT level attacks and compromise. Other properties will also be considered such as the total cost, the required resources, the user interface, etc. (20%).
For registration and contest related inquiries, please email: email@example.com. Please add “HDC2017” to the subject line of any email. We encourage you to register as early as possible and no later than the deadline outlined, because free FPGA boards will be limited to the first 25 teams on a first come first served basis.
To register your team, please provide the following information:
Affiliation of the team/contestant(s)
Names of team members
One correspondence e-mail address for the team
Name of the team
A short paragraph of no more than 250 words about your design idea and the problem you are planning to solve.
Gmail address (Technical support will be provided through Google Groups)
|Yiyu Shi||University of Notre Dame||Chair|
|Yier Jin||University of Central Florida||Co-Chair|
|Abdullah Raouf||Lattice Semiconductor||Industry Liaison|
|Claude Moughanni||Lattice Semiconductor||Industry Liaison|
|Bei Yu||Chinese University of Hong Kong||Web Support|