Hall of Fame

Computer Engineering (CE) students win the champion of the ICCAD 2012 International CAD Contest on the topic of Functional ECO

Congratulations to Xing WEI, Tak Kei LAM , and Yi DIAO, supervised by Prof. Yu-Liang David WU won the first place of the ICCAD 2012 International CAD Contest on the topic of Functional ECO.

 

There are two kinds of bugs in the modern computing facilities: software bugs and hardware bugs. A software bug can be fixed by downloading a correction patch; but an ASIC hardware bug can¡¦t. Engineering change order (ECO) is the request (or requirement) of changing (correcting) a hardware specification, from buggy to bug-free in a late design stage where the whole CAD (also named EDA) design cycle is almost or already completed. Such an EDA cycle (from RTL, logic synthesis, to place and route) for today's chip design would typically take several months (e.g. 3 full months for today's SoC FPGA chip to complete). Here are the typical problems the hardware designers then are facing: (1) The problematic signal lines or gates are likely to have vanished in the "sea of logic" after synthesis - simply no way to trace; (2) Even a just one line change in RTL could produce a very different netlist after iterations of synthesis - implying that tuning the previously done place and route outcome to form a correct circuit is quite difficult, no matter by hands or by tools.

 

To avoid the retaking of another several months painful EDA cycle, it is the time to call an ECO tool instead to generate a minimal hardware patch to correct the buggy netlist. It is highly desirable that the bugs can be fixed at this (pre-mask) functional ECO process, for in a post-mask re-spin (bug-fixing) process a typical expense of USD 20M and an extra 35% of the whole chip design cycle time could be needed today. (Due to the high complexity of an ECO process, the list (rental) price of a today's well-known commercial ECO tool would be about USD400k per license per year.)

 

Since the functional ECO process has become an emerging critical problem for today's increasingly more complicated IC designs, this problem is sponsored by Cadence as the first topic for ICCAD 2012 international CAD Contest. Partly attributed by a home-brew new logic synthesis technique invented by the group, the ECO tool HillWalker developed by students Xing WEI, Tak Kei LAM , and Yi DIAO, guided by Prof. Yu-Liang (David) WU, has won the first place of this contest. In this quite popular EDA contest topic (attracted 33 international competing teams), our students earned over 40% higher total scores than other teams. Without applying any exhaustive search methods, HillWalker hits best solutions at a rate about 80% on the contest industrial benchmarks (provided and verified by Cadence).