Research Excellence

Chun Hok Ho, Chi Wai Yu, Philip Leong, Wayne Luk and Steven Wilton received the Stamatis Vassiliadis Award for Outstanding Paper in the International Conference on Field Programmable Logic and Applications (FPL) in Amsterdam

Chun Hok Ho, Chi Wai Yu, Philip Leong, Wayne Luk and Steven Wilton received the Stamatis Vassiliadis Award for Outstanding Paper in the International Conference on Field Programmable Logic and Applications (FPL) in Amsterdam. The paper, entitled "Domain-Specific Hybrid FPGA: Architecture and Floating-Point Applications" proposes an architecture that can achieve a 2.5 times speed and 18 times area improvement over conventional FPGA devices.

 

The FPL conference is the first and largest on FPGA design and applications. The first two authors are graduates from the Department of Computer Science and Engineering at the Chinese University of Hong Kong, both having been supervised by Prof. Philip Leong who is the Director of the Custom Computing Laboratory. Mr Ho and Mr Yu are now doing their PhD degrees at Imperial College.

 

ABSTRACT
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine-grained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are used for implementing datapaths; the precise amount of each type of resources can be customised to suit specific application domains. Issues and challenges associated with the design flow and the architecture modelling are addressed. Examples of the proposed architecture for speeding up floating point applications are illustrated. Current results indicate that the proposed architecture can achieve 2.5 times improvement in speed and 18 times reduction in area on average, when compared with traditional FPGA devices on selected floating point benchmark circuits.