卓越研究

何循學,余志偉,梁恆惠教授,Wayne Luk和Steven Wilton在阿姆斯特丹舉行的Field Programmable Logic and Applications (FPL)國際會議上以其優秀的論文獲得Stamatis Vassiliadis 獎

何循學,余志偉,梁恆惠教授,Wayne Luk和Steven Wilton在阿姆斯特丹舉行的Field Programmable Logic and Applications (FPL)國際會議上以其優秀論文獲得the Stamatis Vassiliadis 獎。論文題為“Domain-Specific Hybrid FPGA: Architecture and Floating-Point Applications”。論文提出一個架構,該架構與比傳統FPGA設備相比,能改善高達2.5倍速度和18倍面積。

 

FPL會議是FPGA設計和應用方面最早和最大型的會議。論文作者何循學,余志偉是香港中文大學計算機科學與工程學系畢業生,兩人一直由Custom Computing實驗室主任梁恆惠教授指導。兩位同學目前正在帝國理工大學攻讀博士學位。

 

論文摘要:
This paper presents a novel architecture for domain-specific FPGA devices. This architecture can be optimised for both speed and density by exploiting domain-specific information to produce efficient reconfigurable logic with multiple granularity. In the reconfigurable logic, general-purpose fine-grained units are used for implementing control logic and bit-oriented operations, while domain-specific coarse-grained units and heterogeneous blocks are used for implementing datapaths; the precise amount of each type of resources can be customised to suit specific application domains. Issues and challenges associated with the design flow and the architecture modelling are addressed. Examples of the proposed architecture for speeding up floating point applications are illustrated. Current results indicate that the proposed architecture can achieve 2.5 times improvement in speed and 18 times reduction in area on average, when compared with traditional FPGA devices on selected floating point benchmark circuits.