XU, Qiang

Selected Publications:

• F. Yuan and Q. Xu. SoC Test Architecture Design and Optimization Considering Power Supply Noise Effects. In Proc. IEEE International Test Conference (ITC), paper 26.2, 2008.
• L. Huang, F. Yuan, and Q. Xu. On Reliable Modular Testing with Vulnerable Test Access Mechanisms. In Proc. ACM/IEEE Design Automation Conference (DAC), pages 834-839, 2008.
• Q. Xu, Y. Zhang and K. Chakrabarty. SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. In Proc. ACM/IEEE Design Automation Conference (DAC), pages 676-681, 2007.
• S. Tang and Q. Xu. A Multi-Core Debug Platform for NoC-Based Systems. In Proc. IEEE/ACM Design, Automation, and Test in Europe (DATE), pages 870-875, 2007.
• Q. Xu and N. Nicolici. DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Transactions on Computers, 55:470-485, Apr. 2006.