XU, Qiang

Selected Publications:

• Q. Xu and N. Nicolici. Modular and Rapid Testing of SOCs with Unwrapped Logic Blocks. IEEE Transactions on VLSI Systems, 13:1275-1285, Nov 2005.
• Q. Xu and N. Nicolici. Modular SOC Testing with Reduced Wrapper Count. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 24:1894-1908, Dec. 2005.
• Q. Xu and N. Nicolici. Multi-Frequency TAM Design for Hierarchical SOCs. IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, 25:181-196, Jan. 2006.
• Q. Xu and N. Nicolici. DFT Infrastructure for Broadside Two-Pattern Test of Core-Based SOCs. IEEE Transactions on Computers, 55:470-485, Apr. 2006.
• Q. Xu and N. Nicolici. Wrapper Design for Testing IP Cores with Multiple Clock Domains. In Proc. IEEE/ACM Design Automation and Test in Europe (DATE) Conference and Exhibition, pages 416-421, 2004. Received Best Paper Award.