Silicon Synthesis and Fast Circuit Interconnect Optimisation Techniques
(Y. L. Wu)

In the deep sub-micron (<0.10 micron feature size) VLSI technology, the interconnect (wiring) delay of the circuit will increase from ~20% (in 1.0 micron technology) of the total chip delay to as high as 80% in deep sub-micron chips. Therefore, silicon conscious methodologies that incorporate both the layout and logic knowledge together will be a crucial issue for developing the deep sub-micron design automation tools. Though some techniques like gate sizing, buffer insertion, net splitting, gate duplication, and wire sizing are also useful in fixing these timing violations, there are situations that simply applying rewiring for certain target wires can do equally or even better for area, delay, and many other optimization improvements. The objective of this project is to develop a flexible, general-purpose interconnect synthesis framework in order to rewire spotted target wires or logic for various optimization needs. We will integrate the edging parts of various rewiring techniques, including our recently developed fast Graph-Based Alternative Wiring (GBAW) technique, to form a flexible framework adaptable to various DA optimization stages starting from logic synthesis, floorplanning, partitioning, to place and route.