Optimal Switching Box Design for Communication Networks, Embedded PLD/FPGAs and System-On-a-Chip (SoC) IP Cores
(Y. L. Wu)

System-On-a-Chip (SoC) has become a mainstream technology for VLSI designs. Allowing post-fabrication changes therefore becomes a more and more desirable objective since no matter how seamless the SoC design flow is made, and no matter how careful the experienced designers are, the need and cost of making redesigns or corrections after fabrication is largely increased. Integrating programmable logic cores together with ASIC circuit inside an SoC chip is thus deemed a promising solution for this new direction. However, one of the basic challenges still lies in the design optimality of the programmable logic cores themselves. In this project, we aim to develop a set of reconfigurable IP (Intellectual Proprietary) Cores and their corresponding CAD tool systems for SoCs. Making a good use of the advantages of our recently invented (patentable) optimal switching box designs, we plan to produce a set of high-performance SoC IP Cores of: (i) Optimal group telecommunication switching boxes (ii) Scalable FPGA blocks, (iii) On-Chip-Networks for CPU-Memory-I/O switching chipsets. These products are expected to be of high tangibility and technology edge with a good chance of generating new and wide commercial applications.