Interconnect-synthesis based EDA Flow for ASIC and FPGA Designs
(Y. L. Wu)

A digital circuit is basically composed of circuit elements (e.g. gates) and signal-wires interconnecting them. Under the continual scaling down on transistor sizes to 90-, 65- and 45-nano-technologies, the timing closure problem of contemporary IC designs has become an ever tough challenge. Because under such technologies, the wiring delay has become a much more dominating factor (over 80% of the total delay) compared to the delay attributed to cell components alone. However, unfortunately and ironically, most of today's ASIC physical design tools are still virtually built without a wire-conscious logic transformation methodology. Consequently, solutions for this timing closure problem are confined to trivial techniques like adding buffers, gate-resizing,.. etc., whose exercise will inevitably increase chip area further and still yet depending on the availability of the scarce left-over chip space.

Rewiring is a novel and proved-effective wire-conscious technique used to add some new wire/gates so as to make some problem-causing wires/gates redundant and removable while with the circuit functions maintained. With the rewiring technique applied in the physical design phases, the logic view and layout information can then be tightly bridged together, which introduces a new dimension for design optimization and further refinements under a much less cost. Our technique can be universally applied to both combinational and sequential circuits for ASIC and FPGA Designs, which is hardly obtainable by any other single EDA technique.