|
VLSI/CAD Laboratory
(Y. L. Wu, P. H. W. Leong and F. Y. Young)
Very Large Scale Integration (VLSI) provides a means to embody
large amount of circuitry in a very compact package. VLSI
has played a critical role in the recent technological revolution
and this role will continue to grow due to the ever increasing
demand for more powerful and more cost-effective components.
It is well known that, over the years, the complexity of VLSI
systems has grown exponentially due to the continual shrinkage
of physical device sizes and the improvement of fabrication
techniques. Therefore, a systematic design approach is needed
not only for fast turn-around time but also to reduce likelihood
of errors. Also, the prevalence of mobile computing has made
power-consumption a major concern in the design of many VLSI
systems.
The purpose of our VLSI/CAD research is to address these issues.
Its main focus is the development of methods and algorithms that
would systematically produce reliable, energy-efficient,
high-performance VLSI systems. To demonstrate the practicality
of these paradigms, prototypes are designed, fabricated, and
evaluated.
In the VLSI/CAD algorithmic area, current activities include research
on floorplanning and on routing problems and switch module design problems in FPGA's (Field Programmable Logic Arrays). Due to low prototyping cost and short production time, FPGA's (Field Programmable Logic Arrays) are viable alternatives to full-custom designs in many applications. But routing has been a serious problem in FPGA's due to the limited availability of routing resources. In addition to studying new routing algorithms, more versatile switch-module designs are also
under investigation. These designs would enable more flexible
routing, hence higher routing completion rate.
Looking ahead to the years to come, when it is expected that the
very deep sub-micron VLSI technology will be on
demand, efforts have begun to develop a new generation of design
automation tools. Since the interconnect delay of a circuit will
increase from about ~20% (in 1.0 micron technology) of the total chip delay to as high as 80% in deep sub-micron chips, most current physical and logic design optimisation techniques - which consider mainly gate delays - will be ineffective or even incorrect in producing desirable results for the new technology. Therefore, interconnect issues like delay modelling, routability, buffer insertions, circuit retiming, etc., should be considered as early as possible in floorplanning and other designing stages. Silicon-conscious methodologies that incorporate both layout and logic knowledge are needed to produce the high-performance circuits of the future.
|
