|Title:||Machine Learning on Chips: From Design Acceleration to Computation Acceleration|
|Date:||December 15, 2017 (Friday)|
|Time:||4:00 p.m. - 5:00 p.m.|
|Venue:||Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
|Speaker:||Prof. Bei Yu
Department of Computer Science and Engineering
The Chinese University of Hong Kong
Machine learning is a powerful technique that can derive knowledge from large data set, and provide prediction and modeling. Since VLSI chip designs have extremely high complexity and gigantic data, recently there has been a surge in applying and adapting machine learning to accelerate the design closure. In this talk, we focus on some key techniques and recent developments of machine learning on chips. Three design acceleration techniques and related applications will be covered: sparse representation, deep convolutional network; active learning based Pareto curve learning. We will also introduce our very recent work on accelerating convolution computation.
Prof. Bei Yu received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Texas at Austin in 2014. He is currently an Assistant Professor in the Department of Computer Science and Engineering, The Chinese University of Hong Kong. He has served in the editorial boards of Integration, the VLSI Journal and IET Cyber-Physical Systems: Theory & Applications. He has received four Best Paper Awards at ISPD 2017, SPIE Advanced Lithography Conference 2016, ICCAD 2013, and ASPDAC 2012, three other Best Paper Award Nominations at DAC 2014, ASPDAC 2013, ICCAD 2011, and four ICCAD/ISPD contest awards.
Enquiries: Ms. Crystal Tam at tel. 3943 8439
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar.