|Title:||Using Machine Learning for Bug classification in Design Verification|
|Date:||December 5, 2016 (Monday)|
|Time:||3:00 p.m. - 4:00 p.m.|
|Venue:||Room 1009, William M. W. Mong Engineering Building (ERB 1009),
The Chinese University of Hong Kong,
|Speaker:||Prof. Ansuman Banerjee
Advanced Computing and Microelectronics Unit
Indian Statistical Institute (ISI) Kolkata
Unit testing and verification constitute an important step in the validation life cycle of large and complex multi-component designs. Many unit validation methods often suffer from the problem of false negatives, when they analyze a component in isolation and look for errors. It often turns out that some of the reported unit failures are infeasible, i.e. the valuations of the component input parameters that trigger the failure scenarios, though feasible on the unit in isolation, cannot occur in practice considering the integrated design, in which the unit-under-test is instantiated. In this talk, we consider this problem in the context of a multi-component design, with a set of unit failures reported on a specific unit. We present an automated two-stage failure scenario classification and prioritization strategy that can filter out false negatives and cluster them accordingly. The use of classical artificial intelligence and program analysis techniques in conjunction with formal verification helps in developing new frameworks for reasoning and deduction, which appear promising for a wide variety of problems.
Ansuman Banerjee is currently serving as an Associate Professor at the Advanced Computing and Microelectronics Unit, Indian Statistical Institute (ISI) Kolkata. His research interests include design automation for embedded systems, hardware-software verification, VLSI CAD, and automata theory. Ansuman received his Ph.D. from IIT Kharagpur. Prior to joining ISI, he served as a researcher in the Computer Science department at National University of Singapore, and worked for Interra Systems India Pvt. Ltd., where he worked as part of the synthesis and verification team.
Enquiries: Miss Ricola Lo at tel 3943 8440
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar.