|Title:||Recent Research Development in Flip-flop Clustering|
|Date:||September 2, 2016 (Friday)|
|Time:||4:00 p.m. - 5:00 p.m.|
|Venue:||Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
|Speaker:||Prof. Iris Hui-Ru Jiang
Department of Electronics Engineering
National Chiao Tung University, Taiwan
Clock power is the major contributor to dynamic power for modern IC design. Recently, flip-flop clustering has been proven to be an effective way to reduce clock power. Flip-flop clustering can be applied to high performance CPUs as well as low power designs. This technique can be performed during synthesis, during placement, and post-placement. In this talk, we summarize recent research development in flip-flop clustering and discuss future directions.
Iris Hui-Ru Jiang received her B.S. and Ph.D. degrees in electronics engineering from National Chiao Tung University, Hsinchu, Taiwan. She is currently a Professor at the Department of Electronics Engineering at National Chiao Tung University, Taiwan. Her research interests lie in the field of Electronic Design Automation with an emphasis on physical design for nanometer ICs, including interaction between logic synthesis and physical design, timing analysis and optimization, design for manufacturability, and EDA applications to emerging technologies. She received Best Paper Award Nomination from ISPD 2013 and DAC 2016 and Best in-track paper from ICCAD 2014. She and her students received the first place award at 2012 CAD Contest at ICCAD, and one first place award and two third place awards at TAU Timing Analysis Contest. She has served on technical program committees of EDA conferences at a variety of tracks, including logic synthesis, verification, physical design, and design for manufacturability tracks at ICCAD, ISPD, ASP-DAC, IWLS, and SLIP. She has also served as an associate editor of IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD) and the chair of IEEE CEDA DATC (Technical Committee of Design Automation). She organized CAD contest at ICCAD from 2012 to 2014, which is recognized as the largest worldwide EDA research contest.
Enquiries: Miss Ricola Lo at tel 3943 8440
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar.