The Chinese University of Hong Kong
Department of Computer Science and Engineering


Title: Transient device-performance fluctuation: efficient measurement and statistical modeling for predicting the lifetime of ICs
Date: August 30, 2016 (Tuesday)
Time: 3:00 p.m. - 3:30 p.m.
Venue: Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
Shatin, N.T.
Speaker: Prof. Takashi Sato
Graduate School of Informatics
Kyoto University, Kyoto, Japan



As the dimension of semiconductor devices becomes smaller, reliability of circuits and its variation are becoming great concerns in chip design.Quantitative evaluations on the basis of measurement data are required for predicting the lifetime of designed chips.Among various degradation phenomena, bias temperature instability (BTI) is considered as most influential upon long term reliability of the circuits.

The threshold voltage of a device increases gradually under BTI stress, which leads to decreased device current.Considering the effect of BTI, the chip that passed the initial functional test conducted after production time may fail later during field operation. Modeling and estimation of device lifetime is definitely important. However, even under an increased stress condition, a long measurement time is required, making BTI modeling difficult.Much longer time is required if one wants to collect degradation on a large number of devices, to build a statistical degradation model.

In this talk, a circuit structure, called BTIarray, and its measurement results are reviewed.The circuits are scalable in terms of the number of target devices, facilitating the efficient collection of degradation data on a large number of devices.With this circuit, degradation measurements of 4k devices has become possible, which can be used for statistical aging characterization. Approaches that try to measure/estimate/predict the lifetime of a given chip are also explained.



Takashi Sato received B. E. and M. E. degrees from Waseda University, Tokyo, Japan, and a Ph. D. degree from Kyoto University, Kyoto, Japan. He was with Hitachi, Ltd., Tokyo, Japan, from 1991 to 2003, with Renesas Technology Corp., Tokyo, Japan, from 2003 to 2006, and with the Tokyo Institute of Technology, Yokohama, Japan. In 2009, he joined the Graduate School of Informatics, Kyoto University, Kyoto, Japan, where he is currently a professor.He was a visiting industrial fellow at the University of California, Berkeley, from 1998 to 1999. His research interests include CAD for nanometer-scale LSI design, fabrication-aware design methodology, and performance optimization for variation tolerance.Dr. Sato is a member of the IEEE and the Institute of Electronics, Information and Communication Engineers (IEICE).He received the Beatrice Winner Award at ISSCC 2000 and the Best Paper Award at ISQED 2003.


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