|Title:||Power Optimization for VLSI Circuits|
|Date:||July 30, 2015 (Thursday)|
|Time:||3:30 p.m. - 4:30 p.m.|
|Venue:||Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
|Speaker:||Dr. Peiyi Zhao
Integrated Circuit and Embedded Systems Lab
Power consumption is the bottleneck of system performance and is listed as one of the top three challenges in ITRS. This presentation first gives a brief overview of power consumption and its environmental and financial Impact. Then it will review circuit level power optimization methods. Finally it will give a case study of dual edge flip flop for dual edge clocking system.
Dr. Peiyi Zhao received a B.S. in Information and Electronics from Zhejiang University in 1987 and he received Ph.D in Computer Engineering from the Center for Advanced Computer Studies of University of Louisiana, Lafayette, U.S.A, 2005. He was an assistant professor in Chapman University, Orange, CA, USA, from 2005-2012. He is currently an associate professor in Integrated Circuit and Embedded Systems Lab in Chapman University. Dr. Zhao's main research area is low power/energy aware integrated circuit design. Schematics of two of his low power/low energy integrated circuit designs have been included in Chapter 10 of a leading integrated circuit text book, "CMOS VLSI Design", W Neil, D. Harris, 4th Edition, Addison Wesley, 2010. His work has been published in IEEE Transaction on Very Large Scale Integration Systems and IEEE conferences. He has been awarded the Joint Research Fund for Overseas Chinese Scholars from National Natural Science Foundation of China (NSFC), 2013-2014. He has received the Achievement Award for Excellence in Scholarly activity/Creativity from Chapman University, in 2010.
Enquiries: Miss Evelyn Lee at tel 3943 8444
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar.