The Chinese University of Hong Kong
Department of Computer Science and Engineering


Title: Cross-Layer Design for Manufacturability and Reliability in Extreme Scaling and Beyond
Date: January 8, 2015 (Thursday)
Time: 10:30 a.m. - 11:30 a.m.
Venue: Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong,
Shatin, N.T.
Speaker: Dr. David Z. Pan
Department of Electrical and Computer Engineering
The University of Texas at Austin



As the CMOS feature enters the era of extreme scaling (14nm, 11nm and beyond), the IC manufacturability challenges are exacerbated, due to multiple patterning and other emerging lithography technologies. Meanwhile, the vertical scaling with 3D-IC integration using through-silicon-vias (TSVs) has gained tremendous interest and initial industry adoption, but TSV involves disruptive manufacturing technologies that require new modeling and design techniques for reliable 3D IC integration. Furthermore, new devices/materials such as nanophotonics are making their headways to on-chip VLSI integration. All these require new design and process technology co-optimizations. This talk will present some recent results from my research group to push the envelope using multiple patterning lithography as well as other emerging technologies, such as 3D-IC and optical interconnects. Cross-layer modeling and CAD tool/methodologies will be discussed to achieve future heterogeneous and reliable circuits and system integration.



David Z. Pan received his BS degree from Peking University, and MS/PhD degrees from UCLA. He was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. He is currently the Engineering Foundation Professor at the Department of Electrical and Computer Engineering, UT Austin. He has published over 200 refereed journal and conference papers. He has served in many journal editorial boards (TCAD, TVLSI, TCAD-I, TCAS-II, TODAES, SCIS, JCST, etc.) and conference organizing/program committees (DAC, ICCAD, DATE, ASPDAC, ISLPED, ISPD, etc.). He is a working group member of the International Technology Roadmap for Semiconductor (ITRS). He has received a number of awards, including the SRC 2013 Technical Excellence Award, 11 Best Paper Awards (ISPD 2014, ICCAD 2013, ASPDAC 2012, ISPD 2011, IBM Research 2010 Pat Goldberg Memorial Best Paper Award in CS/EE/Math, ASPDAC 2010, DATE 2009, ICICDT 2009, SRC Techcon in 1998, 2007 and 2012), DAC Top 10 Author Award in Fifth Decade, DAC Prolific Author Award, Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), ISPD Routing Contest Awards (2007), eASIC Placement Contest Grand Prize (2009), ICCAD 12 and ICCAD13 CAD Contest Awards, among others. He is an IEEE Fellow.


Enquiries: Miss Evelyn Lee at tel 3943 8444

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