| Title: | A test and validation access scheme in a complex IP/SOC environment |
| Date: |
February 9, 2012 (Thursday)
|
| Time: |
2:30 p.m. - 3:30 p.m.
|
| Venue: |
Room 121, 1/F, Ho Sin-hang Engineering Building,
The Chinese University of Hong Kong, Shatin, N.T. |
| Speaker: |
Mr. Jun Qian
Director, China DFX lead AMD, Shanghai China |
There are many challenges in developing large SOC chips to meet quality, cost requirements and TTM. These challenges are manifested when we push the process technology to the edge. New product development requires sophisticated test and debug schemes.
In this talk, we will discuss the challenges we face in the development of a very large scale SOC following the guideline of IP/SOC model in the area of design for test, design for debug. We will discuss the modular approach, the test and validation access scheme in detail.
BIOGRAPHY:
Mr. Jun Qian is currently managing AMD's DFX teams in China region between Shanghai and Beijing. He has been working in IC industry for 18 years with responsibility ranging from design, design for test and program management. He has collected rich experience in the area of design for test and design for debug.
Mr. Qian holds a MS degree in electrical and computer engineering from University of Iowa.
Enquiries: Miss Temmy So at tel 3943 8444
For more information, please refer to http://www.cse.cuhk.edu.hk/seminar