Device Usage Page (usage_statistics_webtalk.html)

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software_version_and_target_device
betaFALSE build_version1682563
date_generatedFri Mar 17 12:26:26 2017 os_platformWIN64
product_versionVivado v2016.3 (64-bit) project_idda67758af011426a9970563f3782b378
project_iteration35 random_id48d3209967525bf4b886b153b0168219
registration_id180155248_1777505402_210595848_646 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg484 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i5-4690 CPU @ 3.50GHz cpu_speed3491 MHz
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
system_ram4.000 GB total_processors1

vivado_usage
gui_resources
abstractcombinedpanel_add_element=1 abstractcombinedpanel_remove_selected_elements=1 basedialog_cancel=33 basedialog_ok=3
basedialog_yes=35 cmdmsgdialog_ok=4 constraintschooserpanel_add_files=1 createsrcfiledialog_file_name=1
definemodulesdialog_define_modules_and_specify_io_ports=25 filesetpanel_file_set_panel_tree=11 flownavigatortreepanel_flow_navigator_tree=52 gettingstartedview_create_new_project=1
hardwaretreepanel_hardware_tree_table=3 hcodeeditor_blank_operations=7 hcodeeditor_commands_to_fold_text=3 hcodeeditor_diff_with=6
mainmenumgr_edit=10 mainmenumgr_export=2 mainmenumgr_file=8 mainmenumgr_import=2
mainmenumgr_open_recent_file=5 mainmenumgr_open_recent_project=3 pacommandnames_auto_connect_target=1 pacommandnames_open_hardware_manager=1
partchooser_board_vendor_chooser=1 partchooser_boards=2 programdebugtab_open_target=1 programdebugtab_program_device=35
programfpgadialog_program=35 projectnamechooser_choose_project_location=1 projectnamechooser_project_name=1 rdicommands_copy=8
rdicommands_cut=3 rdicommands_paste=6 rdicommands_undo=4 srcchooserpanel_add_hdl_and_netlist_files_to_your_project=1
srcchooserpanel_create_file=1
java_command_handlers
addsources=2 autoconnecttarget=1 editundo=4 launchprogramfpga=35
newhardwaredashboard=1 newproject=1 openhardwaremanager=3 programdevice=4
projectsettingscmdhandler=1 runbitgen=37 savefileproxyhandler=3 viewtaskprojectmanager=2
other_data
guimode=1
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=0 export_simulation_ies=0
export_simulation_modelsim=0 export_simulation_questa=0 export_simulation_riviera=0 export_simulation_vcs=0
export_simulation_xsim=0 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=VHDL srcsetcount=1 synthesisstrategy=Vivado Synthesis Defaults
target_language=VHDL target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bufg=3 carry4=100 fdre=133 gnd=1
ibuf=1 ldce=3 ldpe=2 lut1=143
lut2=414 lut3=2 lut4=21 lut5=16
lut6=13 obuf=14 vcc=2
pre_unisim_transformation
bufg=3 carry4=100 fdre=133 gnd=1
ibuf=1 ldce=3 ldpe=2 lut1=143
lut2=414 lut3=2 lut4=21 lut5=16
lut6=13 obuf=14 vcc=2

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-ruledecks=default::[not_specified] -upgrade_cw=default::[not_specified]
results
pdrc-153=2 zps7-1=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
results
timing-17=100 timing-20=5

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") clocks=0.000921 confidence_level_clock_activity=Low
confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium confidence_level_io_activity=High
confidence_level_overall=Low customer=TBD customer_class=TBD devstatic=0.121465
die=xc7z020clg484-1 dsp_output_toggle=12.500000 dynamic=0.001453 effective_thetaja=11.5
enable_probability=0.990000 family=zynq ff_toggle=12.500000 flow_state=routed
heatsink=none i/o=0.000064 input_toggle=12.500000 junction_temp=26.4 (C)
logic=0.000242 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000 mgtavcc_total_current=0.000000
mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000 mgtavtt_total_current=0.000000
mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000 mgtvccaux_total_current=0.000000
mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000 on-chip_power=0.122917
output_enable=1.000000 output_load=5.000000 output_toggle=12.500000 package=clg484
pct_clock_constrained=0.000000 pct_inputs_defined=100 platform=nt64 process=typical
ram_enable=50.000000 ram_write=50.000000 read_saif=False set/reset_probability=0.000000
signal_rate=False signals=0.000226 simulation_file=None speedgrade=-1
static_prob=False temp_grade=commercial thetajb=7.4 (C/W) thetasa=0.0 (C/W)
toggle_rate=False user_board_temp=25.0 (C) user_effective_thetaja=11.5 user_junc_temp=26.4 (C)
user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W) vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000
vccadc_total_current=0.020000 vccadc_voltage=1.800000 vccaux_dynamic_current=0.000000 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000 vccaux_io_voltage=1.800000 vccaux_static_current=0.018814
vccaux_total_current=0.018814 vccaux_voltage=1.800000 vccbram_dynamic_current=0.000000 vccbram_static_current=0.000443
vccbram_total_current=0.000443 vccbram_voltage=1.000000 vccint_dynamic_current=0.001453 vccint_static_current=0.007466
vccint_total_current=0.008919 vccint_voltage=1.000000 vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000
vcco12_total_current=0.000000 vcco12_voltage=1.200000 vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000
vcco135_total_current=0.000000 vcco135_voltage=1.350000 vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000
vcco15_total_current=0.000000 vcco15_voltage=1.500000 vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000
vcco18_total_current=0.000000 vcco18_voltage=1.800000 vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000
vcco25_total_current=0.000000 vcco25_voltage=2.500000 vcco33_dynamic_current=0.000000 vcco33_static_current=0.001000
vcco33_total_current=0.001000 vcco33_voltage=3.300000 vcco_ddr_dynamic_current=0.000000 vcco_ddr_static_current=0.000000
vcco_ddr_total_current=0.000000 vcco_ddr_voltage=1.500000 vcco_mio0_dynamic_current=0.000000 vcco_mio0_static_current=0.000000
vcco_mio0_total_current=0.000000 vcco_mio0_voltage=1.800000 vcco_mio1_dynamic_current=0.000000 vcco_mio1_static_current=0.000000
vcco_mio1_total_current=0.000000 vcco_mio1_voltage=1.800000 vccpaux_dynamic_current=0.000000 vccpaux_static_current=0.010330
vccpaux_total_current=0.010330 vccpaux_voltage=1.800000 vccpint_dynamic_current=0.000000 vccpint_static_current=0.016396
vccpint_total_current=0.016396 vccpint_voltage=1.000000 vccpll_dynamic_current=0.000000 vccpll_static_current=0.003000
vccpll_total_current=0.003000 vccpll_voltage=1.800000 version=2016.3

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=3 bufgctrl_util_percentage=9.38
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsps_available=220 dsps_fixed=0 dsps_used=0 dsps_util_percentage=0.00
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=0 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=0 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=0 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=0 block_ram_tile_util_percentage=0.00
ramb18_available=280 ramb18_fixed=0 ramb18_used=0 ramb18_util_percentage=0.00
ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=0 ramb36_fifo_util_percentage=0.00
primitives
bufg_functional_category=Clock bufg_used=3 carry4_functional_category=CarryLogic carry4_used=100
fdre_functional_category=Flop & Latch fdre_used=133 ibuf_functional_category=IO ibuf_used=1
ldce_functional_category=Flop & Latch ldce_used=3 ldpe_functional_category=Flop & Latch ldpe_used=2
lut1_functional_category=LUT lut1_used=19 lut2_functional_category=LUT lut2_used=414
lut3_functional_category=LUT lut3_used=2 lut4_functional_category=LUT lut4_used=21
lut5_functional_category=LUT lut5_used=16 lut6_functional_category=LUT lut6_used=13
obuf_functional_category=IO obuf_used=14
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=333 lut_as_logic_util_percentage=0.63
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=133 register_as_flip_flop_util_percentage=0.13
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=5 register_as_latch_util_percentage=<0.01
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=333 slice_luts_util_percentage=0.63
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=138 slice_registers_util_percentage=0.13
fully_used_lut_ff_pairs_fixed=0.13 fully_used_lut_ff_pairs_used=0 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=0
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=333 lut_as_logic_util_percentage=0.63
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=0 lut_as_memory_util_percentage=0.00
lut_as_shift_register_fixed=0 lut_as_shift_register_used=0 lut_ff_pairs_with_one_unused_flip_flop_fixed=0 lut_ff_pairs_with_one_unused_flip_flop_used=7
lut_ff_pairs_with_one_unused_lut_output_fixed=7 lut_ff_pairs_with_one_unused_lut_output_used=5 lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=7 lut_flip_flop_pairs_util_percentage=0.01 slice_available=13300 slice_fixed=0
slice_used=134 slice_util_percentage=1.01 slicel_fixed=0 slicel_used=100
slicem_fixed=0 slicem_used=34 unique_control_sets_used=9 using_o5_and_o6_fixed=9
using_o5_and_o6_used=152 using_o5_output_only_fixed=152 using_o5_output_only_used=0 using_o6_output_only_fixed=0
using_o6_output_only_used=181
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=968405 bogomips=0 bram18=0 bram36=0
bufg=0 bufr=0 congestion_level=0 ctrls=9
dsp=0 effort=2 estimated_expansions=268464 ff=138
global_clocks=3 high_fanout_nets=0 iob=15 lut=339
movable_instances=744 nets=865 pins=4109 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=2 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg484-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -shreg_min_size=default::3 -top=TestVGA
-verilog_define=default::[not_specified]
usage
elapsed=00:00:22s hls_ip=0 memory_gain=443.871MB memory_peak=682.320MB